Capacitance-Voltage (C-V) measurement characterizes the electrical properties of dielectrics, MOS structures, and semiconductor junctions by measuring capacitance as a function of applied DC bias. Principle: Apply DC bias voltage to MOS capacitor or junction while superimposing small AC signal. Measure capacitance at each bias point. Plot C vs V curve. MOS C-V: Three regimes visible in C-V curve: accumulation (high C = oxide capacitance), depletion (C decreases as depletion width grows), inversion (C saturates at minimum). Parameters extracted: Oxide thickness (from accumulation capacitance: Cox = epsilon*A/t), flatband voltage (Vfb), threshold voltage (Vt), doping concentration, interface trap density (Dit). Dit measurement: Interface traps cause stretch-out and frequency dispersion in C-V curves. Conductance method or high-low frequency comparison extracts Dit. Oxide quality: C-V reveals oxide charges - fixed charge, mobile charge, trapped charge. Critical for gate dielectric qualification. High-k dielectrics: C-V on high-k/metal gate stacks measures EOT and evaluates dielectric quality. Junction C-V: Measures doping profile from depletion capacitance vs voltage. Profiling technique for well and channel doping. Equipment: LCR meter or impedance analyzer with probe station. Frequencies typically 1 kHz to 1 MHz. Applications: Gate oxide qualification, process monitoring, device characterization, reliability screening. Test structures: MOS capacitors in scribe lanes or dedicated test chips for inline monitoring.