Cell-Aware Test and ATPG for Intra-Cell Defects

Cell-Aware Test and ATPG for Intra-Cell Defects

Executive Overview

Cell-aware test is a defect-oriented test methodology that generates automatic test pattern generation (ATPG) patterns targeting physical defects located inside standard cells — within the transistors and local interconnect of a NAND gate, flip-flop, or multiplexer — rather than only at the cell's external input and output pins. Conventional stuck-at and transition-delay fault models treat every standard cell as an opaque Boolean primitive: a fault is injected at a pin, and the model assumes any internal defect that changes the cell's logical behavior will show up as one of a small, generic set of pin-level fault effects. That assumption breaks down as cell libraries move to smaller geometries with more densely packed transistors per cell, because a large fraction of real silicon defects — resistive bridges between adjacent internal nodes, partial opens in local interconnect, parametric shifts in a single transistor's drive strength — do not map cleanly onto pin-level stuck-at or transition behavior. Cell-aware test closes this gap by extracting a transistor-level defect list directly from each cell's physical layout, simulating the electrical behavior each defect actually produces, and compiling the results into a cell-specific fault dictionary that ATPG tools use to generate patterns capable of detecting and distinguishing defects that pin-level models miss entirely. This article covers the defect extraction and analog simulation methodology, fault dictionary construction and library characterization, ATPG and pattern compaction integration, diagnosis applications, and the production test-quality trade-offs that determine when cell-aware test is worth its added characterization cost.

Part 1: Why Pin-Level Fault Models Miss Intra-Cell Defects

The Boolean Abstraction and Its Limits

Standard digital test methodology models each cell as a Boolean function with a small number of associated faults per pin — typically stuck-at-0, stuck-at-1, and slow-to-rise/slow-to-fall transition faults. This abstraction is enormously productive because it lets ATPG reason about a whole chip in terms of a manageable, technology-independent fault list rather than the full transistor netlist. The abstraction is valid only to the extent that real defects actually produce one of those modeled pin-level behaviors. For a simple two-transistor inverter this is usually a reasonable approximation: most defect locations inside the cell manifest as a stuck-at or transition fault at the output, since there is little internal structure for a defect's effect to hide behind. As cell complexity grows — a four-input AND-OR-INVERT gate, a scan flip-flop with internal master-slave latches and multiplexed scan-enable logic, a complex multiplexer with a dozen internal transistors — the number of internally distinguishable defect behaviors grows much faster than the number of external pins, and a growing fraction of physically realistic defects produce electrical behavior that no combination of pin-level stuck-at or transition faults reproduces.

Defect Classes That Escape Pin-Level Models

Three defect classes are the primary drivers of the gap. Resistive bridging defects between two internal nodes that are not directly connected in the intended design create a coupling whose logical effect depends on both nodes' simultaneous states — a condition that a single-node stuck-at model cannot express, and that only shows up for specific combinations of the cell's inputs. Partial (resistive) opens in internal interconnect or contacts behave differently depending on the resistance value and the surrounding circuit's drive strength, sometimes acting as a full stuck-at fault, sometimes as a delay-only defect that only a slow, marginal path timing check would catch, and sometimes as an intermittent fault sensitive to voltage and temperature. Transistor-level parametric defects — a threshold-voltage shift, an unintended narrow channel, a missing or extra contact reducing an individual transistor's effective drive strength — degrade a cell's noise margin or switching speed without necessarily flipping its steady-state logic value at all, so they escape both stuck-at and, at weaker severities, even transition-delay detection unless the test specifically targets the affected internal path.

Quantifying the Coverage Gap

The foundational cell-aware test literature (Reddy et al., 2014) reports production fails traced back to intra-cell defect locations that standard pin-level ATPG patterns did not target, even when those patterns achieved high nominal stuck-at or transition-delay fault coverage; those findings helped motivate the methodology in the first place. This is the underlying rationale for cell-aware test: high coverage against an abstracted fault model does not guarantee high coverage against the actual physical defect population, and the gap between the two is expected to grow with cell complexity and with technology scaling that increases the relative frequency of resistive and parametric defect mechanisms versus hard, fully-open or fully-shorted defects. The precise magnitude of this gap is design- and technology-specific and is best established by a design's own failure-analysis and yield-learning data rather than assumed from industry-wide figures.

Part 2: Cell-Internal Defect Extraction and Electrical Modeling

Layout-Based Defect Extraction

Cell-aware characterization begins with the physical layout of each standard cell in the target library, not its logical description. An extraction tool walks the layout and enumerates realistic defect sites: bridging candidates between metal or polysilicon segments that lie within a technology-specific critical distance of each other (the closer two conductors are drawn, the more likely a real process variation — a photoresist bridge, a metal residue, an etch-related short — connects them), open candidates at vias, contacts, and narrow interconnect necks that are statistically prone to voids or incomplete fill, and transistor-level defects such as gate-oxide shorts or source/drain-to-gate bridges identified from the transistor-level layout geometry. The output of this stage is a defect list specific to each cell's physical implementation — two cells with the same Boolean function but different layouts (a different transistor sizing, a different routing choice) generally have different cell-aware defect lists, because the defect list is a property of the physical implementation, not the logic function.

Analog Simulation of Defect Behavior

Each candidate defect from the extraction pass is injected into the cell's transistor-level (SPICE-level) netlist and simulated under the cell's full range of input combinations, since a bridging or resistive defect's electrical effect generally depends on which other transistors in the cell are conducting at the time. For a bridging defect between two nodes, the simulation determines the resulting logic value (or, for a resistive bridge, a range of resistance values and the logic value or a "possible detect" outcome at each) for every input combination the cell can be driven with. This analog simulation step is the computationally expensive core of cell-aware characterization: a cell with N internal defect candidates and 2^k relevant input states (k being the number of independent internal signals affecting the defect's behavior) requires on the order of N × 2^k transistor-level simulations, and full-library characterization for a modern standard-cell library with hundreds of cells and multiple drive strengths per logical function can require millions of individual SPICE runs, which is why cell-aware characterization is typically performed once per library (or per library revision) by the library provider or a specialized characterization team, rather than repeated for every design that uses the library.

Resistance Sweeps and Detection Confidence

Bridging and open defects are rarely ideal short circuits or complete breaks; most real occurrences fall somewhere along a resistance spectrum from a few ohms to effectively open. Characterization sweeps a representative set of resistance values for each bridging and open defect candidate and records, at each resistance, whether the defect produces a clean logic-level fault, a timing-only (delay) fault, or no observable effect within the cell's normal operating margins. This resistance-dependent behavior is the reason a single defect location in a cell-aware fault dictionary is often represented as several distinct fault entries — a low-resistance bridge behaving as a hard fault, a mid-resistance bridge behaving as a delay fault, and a high-resistance bridge falling below the detection threshold entirely — rather than one entry per physical location.

Part 3: Fault Dictionary Construction and Library Characterization

From Simulation Results to a Cell-Aware Fault Model

The simulation results for every defect candidate and every relevant input combination are compiled into a per-cell fault dictionary: a table mapping each internal defect to the set of external input conditions ("excitation conditions") required to activate it and the resulting output behavior needed to observe it. Unlike a stuck-at fault, which requires only a single input combination to sensitize, many cell-aware faults require multiple internal signals to be in specific states simultaneously, which is more constraining for ATPG but also more diagnostic, since a pattern that detects one cell-aware fault often does not detect several other faults in the same dictionary that require different excitation conditions — improving fault resolution for later diagnosis.

Library Characterization Scope and Maintenance

Because the fault dictionary is tied to a specific physical cell implementation, it must be regenerated whenever the cell library changes — a new technology node, a new drive-strength variant, or even a re-layout of an existing cell for density or DFM (design-for-manufacturability) reasons invalidates the previous characterization. Library providers typically deliver the cell-aware fault dictionary as a companion data file alongside the standard timing, power, and layout views already shipped with a cell library, and design teams treat an out-of-date cell-aware dictionary the same way they would treat a stale timing library — as a correctness risk for any test coverage or diagnosis work built on top of it.

Coverage of Library Variants

Modern standard-cell libraries ship many electrically distinct variants of the same logic function — different drive strengths, different threshold-voltage flavors for power/performance trade-offs, and multiple physical layout implementations for routing congestion or DFM reasons. Each variant is, in general, a distinct characterization target, since drive strength changes transistor sizing (and therefore defect sensitivity and resistance thresholds) and a different physical layout changes which nodes are close enough to bridge. Comprehensive library-level cell-aware coverage therefore requires characterizing every variant actually instantiated in production designs, not just one representative cell per logic function.

Part 4: ATPG Integration and Pattern Generation

Fault List Expansion at the Design Level

At the chip level, ATPG expands the per-cell fault dictionaries across every instance of every characterized cell in the design's netlist, producing a design-specific cell-aware fault list that sits alongside (and is typically run in addition to, not instead of) the standard stuck-at and transition-delay fault lists. This expansion can be large — a design instantiating tens of thousands of cells, each with dozens of internal fault dictionary entries, yields a cell-aware fault list an order of magnitude larger than the corresponding pin-level stuck-at list — which is one of the primary practical costs of adopting cell-aware test.

Test Generation and Excitation Constraints

Generating a pattern for a cell-aware fault requires the ATPG engine to satisfy the fault's excitation conditions at the cell's inputs (which may require multiple internal signals to align, unlike a single-input stuck-at excitation), propagate the resulting effect to an observable point (a primary output or a scan flip-flop, exactly as in conventional ATPG), and justify the required input state back through the combinational logic feeding the cell, using the same justification and propagation algorithms as conventional structural ATPG. Because cell-aware excitation conditions are more constrained than pin-level stuck-at conditions, a cell-aware fault is sometimes ATPG-untestable (impossible to excite given the surrounding logic) even when the corresponding pin-level fault at the same cell is fully testable, and distinguishing genuinely untestable cell-aware faults from ones merely requiring more sophisticated pattern generation is an ongoing accuracy concern in cell-aware ATPG tool development.

Pattern Reuse and Incremental Generation

Because a single pin-level stuck-at pattern frequently also happens to excite and detect one or more cell-aware faults as a side effect (the pattern was generated for a different purpose but incidentally satisfies a cell-aware fault's excitation condition), cell-aware ATPG flows typically begin by fault-grading the existing stuck-at and transition-delay pattern set against the cell-aware fault list before generating any new patterns, then generate additional top-up patterns only for the residual cell-aware faults the existing set does not already cover. This incremental approach substantially reduces the number of additional patterns required compared to generating a cell-aware pattern set from scratch.

Part 5: Pattern Compaction and Test Volume Trade-offs

The Pattern Volume Cost of Cell-Aware Coverage

Every additional test pattern increases production test time and, at high volume, test cost — so the pattern volume added by cell-aware top-up generation is under direct commercial pressure to be minimized. Static compaction (merging multiple faults' excitation and propagation requirements into a single pattern when they are mutually compatible) and dynamic compaction (extending a partially-specified pattern to opportunistically detect additional faults during generation) both apply to cell-aware patterns using the same underlying algorithms as conventional ATPG compaction, but cell-aware faults' more constrained excitation conditions generally compact less efficiently than pin-level faults, meaning the pattern count added by a cell-aware pass, while smaller than a full from-scratch cell-aware pattern set, is not negligible.

Selective Cell-Aware Application

Because full-chip cell-aware ATPG can be expensive in both characterization effort and pattern volume, many production flows apply cell-aware test selectively — to safety-critical or high-reliability designs in full, or to a targeted subset of cells (those in known-critical timing paths, those with the highest historical defect-per-million contribution from yield learning, or those in a library with known process sensitivity) for cost-sensitive high-volume designs where exhaustive cell-aware coverage is not economically justified. This selective application requires the yield and quality organization to have some prior basis — typically derived from failure analysis or from a related product's field return data — for prioritizing which cells or cell instances most benefit from cell-aware coverage.

Test Time and ATE Cost Implications

Additional cell-aware patterns translate directly into additional automated test equipment (ATE) time per die, which at high production volumes is a first-order cost driver. Program design typically evaluates cell-aware pattern sets against a target defect-per-million (DPPM) reduction and weighs the marginal test-time cost against the marginal quality improvement, rather than adopting cell-aware test unconditionally — the methodology is a quality lever with a real cost, not a free coverage improvement.

Part 6: Diagnosis and Failure Analysis Applications

Improved Fault Resolution

Because cell-aware fault dictionaries distinguish many internal defect locations and resistance regimes that pin-level models collapse into a single generic fault, a failing pattern's cell-aware diagnosis result narrows the suspect defect location and mechanism far more precisely than a pin-level stuck-at diagnosis can — often down to a specific internal node pair or transistor within a specific cell instance, rather than "somewhere at or near this cell's output." This resolution improvement is one of cell-aware test's most consistently cited benefits independent of its raw coverage contribution, because it directly reduces the physical failure analysis effort (focused ion beam cross-sectioning, electron microscopy) needed to root-cause a field or production fail.

Closing the Loop with Physical Failure Analysis

When physical failure analysis on a returned or production-failing part identifies an actual defect mechanism and location, cell-aware diagnosis results can be checked against that ground truth to validate (or, when they disagree, to debug) both the cell-aware characterization data and the diagnosis algorithm itself. Systematic mismatches between cell-aware diagnosis predictions and physical failure analysis findings are a signal that the underlying defect extraction or electrical characterization for a specific cell or defect class needs to be revisited, making this feedback loop an important quality-control mechanism for the characterization data itself, not just for the chips being tested.

Yield Learning Feedback

Aggregated cell-aware diagnosis results across a large volume of production fails reveal which cells, which internal defect mechanisms, and which physical layout features are disproportionately associated with real yield loss — information that is more actionable for process and design-rule improvement than aggregate pin-level fail-bin statistics, because it points at specific layout geometries (a particular via, a particular minimum-spacing routing configuration) rather than only at a logical fault category.

Part 7: Timing-Aware Cell-Aware Defects and Small-Delay Faults

Resistive Defects as Delay Faults

A subset of cell-aware defects — particularly resistive opens and moderate-resistance bridges — do not change a cell's steady-state logic value at all but do slow its switching speed, sometimes only slightly. These behave as small-delay defects: a functionally correct but marginally slower path that a functional or at-speed test targeting the nominal critical path may not catch, but that becomes a real timing failure under worst-case process, voltage, and temperature corners or after further in-field degradation. Cell-aware characterization's resistance-sweep methodology directly identifies which internal defects fall into this delay-only regime and at what resistance threshold the transition from "logic fault" to "delay fault" to "no effect" occurs, information that pin-level transition-delay fault models cannot provide because they do not model resistance-dependent behavior at all.

Path-Sensitized Cell-Aware Delay Test

Detecting a cell-aware delay defect requires not just exciting the defect (as for a logic fault) but doing so along a timing path with enough slack margin removed — typically the same at-speed, launch-and-capture test infrastructure used for conventional transition-delay ATPG — that the added delay from the defect causes an observable timing failure at the capture flip-flop. Combining cell-aware excitation conditions with at-speed path sensitization is algorithmically more demanding than either technique alone, and tool support for fully integrated cell-aware small-delay ATPG has historically lagged behind cell-aware logic-fault ATPG for this reason.

Reliability and Latent Defect Screening

Small-delay cell-aware defects are of particular interest for reliability screening because a marginal resistive defect that does not fail test today can worsen over field operation (through electromigration, further oxide degradation, or thermal cycling stress) into a hard failure later. Burn-in and other accelerated-stress screening programs increasingly use cell-aware-informed pattern sets specifically to stress and catch these latent, currently-marginal defects before shipment, rather than relying solely on generic elevated-temperature and elevated-voltage stress with conventional pattern sets.

Part 8: Quality Impact and DPPM Reduction

Correlating Cell-Aware Coverage to Field Quality

The methodology's justification rests on a straightforward mechanism rather than a single universal figure: because cell-aware patterns target physical defect behaviors that pin-level fault models cannot represent at all, they can only add coverage relative to a pin-level-only pattern set, never subtract from it. Whether that added coverage translates into a measurable defects-per-million-shipped improvement for a specific design and technology is an empirical question best answered by that design's own data — a controlled DPPM comparison across matched lots, or correlating cell-aware fault coverage against outgoing quality data over enough production volume to be statistically meaningful — rather than assumed from a general industry claim. This is why adoption decisions are typically driven by a design's own reliability requirements and its own quality data (automotive, aerospace, and medical applications tend to weight this most heavily) rather than adopted uniformly across all product segments.

Automotive and High-Reliability Qualification

Automotive semiconductor programs operate under two distinct kinds of pressure that make cell-aware test's value proposition especially relevant, without either one mandating the methodology outright. AEC-Q100 is a component-level qualification standard covering stress testing and reliability qualification for automotive ICs; it does not itself specify a test-pattern methodology, but the demanding outgoing-quality expectations common in automotive supply chains make any technique that closes a real coverage gap — such as cell-aware test — more attractive there than in segments with looser quality requirements. ISO 26262 is a functional-safety standard whose diagnostic-coverage requirements concern a system's ability to detect and react to faults during operation, which is a related but distinct concept from production test's pattern-based defect screening; cell-aware diagnosis's improved fault resolution is useful for the failure-analysis and root-causing work that supports a functional-safety case, but ISO 26262 compliance does not by itself require cell-aware ATPG. In practice, these standards create an environment where the reliability-quality bar rewards closing known coverage gaps, and cell-aware test is one of the techniques available for doing so — rather than being a standards-mandated requirement.

Part 9: Scan-Chain and Production Test Flow Integration

Compatibility with Standard Scan-Based Test

Cell-aware ATPG patterns are generated and applied using the same scan-chain infrastructure (shift-in of test stimulus through scan flip-flops, capture at functional clock speed, shift-out of the response) as conventional stuck-at and transition-delay patterns, requiring no additional design-for-test hardware beyond what a design already implements for standard scan test. This is a significant practical advantage: cell-aware coverage is added as an additional pattern set layered onto an existing scan-based test flow rather than requiring new DFT structures, new silicon area, or new ATE hardware capability.

Fault Simulation and Coverage Signoff

Cell-aware fault coverage is reported and signed off analogously to stuck-at coverage — as a percentage of the cell-aware fault list detected by the final pattern set — but is typically tracked as a separate coverage metric alongside (not merged into) stuck-at and transition-delay coverage numbers, since the fault models measure different things and a single blended percentage would obscure which defect classes remain under-tested. Test engineering signoff criteria increasingly specify minimum cell-aware coverage targets in addition to conventional fault coverage targets for designs where the reliability requirements justify the added characterization and pattern-generation cost.

Production Deployment Considerations

Deploying cell-aware test in a production test program requires the cell library's cell-aware characterization data to be available and current for every cell variant instantiated in the design, ATPG and fault-simulation tool support for cell-aware fault models (available in mainstream commercial ATPG tools from the major EDA vendors), sufficient ATE test-time and pattern-memory budget for the added pattern volume, and a defined coverage target and pass/fail signoff criterion agreed between design, test engineering, and quality organizations before tape-out, since retrofitting cell-aware coverage onto an already-signed-off test program is markedly more disruptive than planning for it from the start of the test development flow.

Summary: Cell-Aware Test as a Defect-Model Discipline

Cell-aware test addresses a specific, well-documented gap in conventional digital test methodology: pin-level stuck-at and transition-delay fault models are a productive abstraction for most defects but systematically miss a meaningful fraction of real intra-cell defects — resistive bridges, partial opens, and parametric transistor-level shifts — whose electrical behavior depends on internal cell structure that the abstraction discards. By extracting a transistor-level defect list from each cell's physical layout, characterizing each defect's behavior through analog simulation across resistance values and input conditions, and feeding the resulting fault dictionary into ATPG and fault simulation alongside conventional fault models, cell-aware test recovers coverage against defect classes and delivers diagnostic resolution that pin-level methods cannot reach. Its adoption is governed by a straightforward cost-benefit calculation — added library characterization effort and added production test pattern volume, weighed against measurable DPPM reduction and improved failure-analysis resolution — which is why it has become closest to standard practice in the reliability-critical market segments (automotive, aerospace, medical) where the quality bar most directly rewards it, while remaining a selectively applied, cost-managed technique elsewhere.

Cell-Aware Defect and Detection Reference

Sources: J. Reddy, R. Zhao, N. Star, S. Lin, N. Devta-Prasanna, W-T. Cheng, M. Gharaybeh, M.E. Amyeen, "Cell-Aware Test," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014 (DOI: 10.1109/TCAD.2014.2323216); "Improving Cell-Aware Test for Intra-Cell Short Defects," Design, Automation & Test in Europe (DATE), 2022 (DOI: 10.23919/DATE54114.2022.9774502); standard industry cell-aware ATPG methodology documentation from major EDA test-tool vendors; AEC-Q100 (automotive IC qualification) and ISO 26262 (functional safety) as background context for automotive test-quality expectations, not as sources mandating cell-aware ATPG specifically.