CFET (Complementary FET) Overview

CFET stacks an NMOS transistor directly on top of a PMOS transistor (or vice versa) in one vertical structure, potentially halving the standard cell area compared to side-by-side nanosheet placement. It is the leading candidate architecture beyond nanosheets for the sub-1nm era.

Why CFET?

• Area Scaling: Conventional CMOS places N and P transistors side by side. CFET stacks them, cutting logic cell footprint by ~30-50%.
• Continued Scaling: When nanosheet area scaling runs out of steam (~2nm node), CFET enables continued density improvement.
• Wiring Simplification: Both transistors share the same vertical footprint, simplifying local interconnect.

Fabrication Approaches

• Monolithic CFET: Build both devices in a single continuous process flow. Grow N-channel and P-channel stacks sequentially, then process together. Cheapest but most technically challenging.
• Sequential CFET: Build bottom device, bond a second wafer on top, then build top device. Easier process integration but adds wafer bonding step and alignment challenges.

Key Challenges

• Thermal Budget: Bottom device must survive all thermal steps used to build the top device.
• Contact Access: Connecting to the buried (bottom) device requires complex routing through or around the top device.
• Alignment: Top and bottom transistors must align precisely (sub-nm overlay).
• Power Delivery: Backside power delivery networks (BSPDN) are critical enablers for CFET.

Timeline

• Research/pathfinding: Active at IMEC, Intel, Samsung, TSMC.
• Expected production: ~2030+ (A14 equivalent node or beyond).