CFET (Complementary FET) is an advanced transistor architecture that vertically stacks nFET and pFET devices to dramatically reduce logic cell area beyond FinFET and nanosheet limits.

What Is CFET?

• Structure: pFET stacked directly above nFET (or vice versa)
• Benefit: 50%+ area reduction vs. lateral placement
• Timeline: Expected at 2nm and beyond (2025+)
• Challenge: Complex process integration, thermal budget management

Why CFET Matters

Horizontal scaling is approaching atomic limits. Vertical stacking provides the next dimension for density improvement.

<svg viewBox="0 0 435 359" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="435" height="359" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">CFET vs. Traditional Layout:</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">Traditional (lateral):        CFET (vertical):</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#6e7681">┌─────┬─────┐</tspan><tspan fill="#c9d1d9">                 </tspan><tspan fill="#6e7681">┌───────────┐</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> pFET</tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">nFET </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">                 </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">   pFET    </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">     </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">     </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">        </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9">        </tspan><tspan fill="#6e7681">├───────────┤</tspan></text><text xml:space="preserve" x="20" y="126.7"><tspan fill="#6e7681">└─────┴─────┘</tspan><tspan fill="#c9d1d9">                 </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">   nFET    </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="145.7"><tspan fill="#c9d1d9">  Wide footprint              </tspan><tspan fill="#6e7681">└───────────┘</tspan></text><text xml:space="preserve" x="20" y="164.7"><tspan fill="#c9d1d9">                              50% smaller</tspan></text><text xml:space="preserve" x="20" y="183.7"></text><text xml:space="preserve" x="20" y="202.7"><tspan fill="#c9d1d9">CFET Cross-Section:</tspan></text><text xml:space="preserve" x="20" y="221.7"><tspan fill="#c9d1d9">     </tspan><tspan fill="#6e7681">══════════════</tspan><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> Gate</tspan></text><text xml:space="preserve" x="20" y="240.7"><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">  p-channel   </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="259.7"><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">├──────────────┤</tspan></text><text xml:space="preserve" x="20" y="278.7"><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">  Isolation   </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="297.7"><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">├──────────────┤</tspan></text><text xml:space="preserve" x="20" y="316.7"><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">  n-channel   </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="335.7"><tspan fill="#c9d1d9">     </tspan><tspan fill="#6e7681">══════════════</tspan><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> Gate (shared or separate)</tspan></text></g></svg>

CFET Integration Challenges:

• Sequential vs. monolithic stacking
• Thermal budget for bottom device
• Contact routing between stacked devices
• Workfunction metal for both polarities