Complementary FET (CFET) is the next-generation transistor architecture that vertically stacks an NMOS device directly on top of a PMOS device (or vice versa) within the same footprint — potentially reducing standard cell area by 40-50% compared to nanosheet FETs by eliminating the lateral N-to-P spacing, representing the most radical transistor architecture change since the introduction of FinFET and the likely device structure for sub-1nm technology nodes.

Why CFET

In current nanosheet technology, NMOS and PMOS transistors sit side by side, separated by an N-to-P space of 40-50nm that is wasted area serving only as an isolation boundary. CFET eliminates this space by stacking NMOS above PMOS vertically — the NMOS and PMOS share the same X-Y footprint, cutting the cell width (and area) roughly in half. This is the most direct path to continued logic density scaling when lateral dimensional scaling (pitch reduction) slows.

CFET Integration Approaches

• Monolithic CFET: Both N and P devices are fabricated in a single continuous process on the same wafer. Requires sequential nanosheet formation (SiGe/Si epitaxial superlattice with separate N and P channel layers), followed by complex process steps to independently access each tier. Maximum density but extreme process complexity.

• Sequential (Bonded) CFET: The bottom device (e.g., PMOS) is fabricated completely. A separate wafer with the top device's channel material is bonded face-down, substrate-removed, and the top device (NMOS) is fabricated on top. Bonded CFET uses proven single-device processes but requires wafer bonding precision and low-temperature top-tier processing (<500°C).

Key Process Challenges

• Independent Gate Control: Each NMOS and PMOS gate must be independently contacted and biased for circuit functionality. Routing separate gate connections from a stacked structure requires creative contact schemes — backside gate contact for the bottom device, front-side for the top device, or split-gate approaches.
• Source/Drain Isolation: The upper and lower source/drain regions are separated by a thin dielectric layer (10-20nm). Any leakage path through this isolation layer degrades circuit performance.
• Interconnect Density: CFET doubles the number of device terminals per unit area, requiring proportionally denser MOL and BEOL connections. Backside power delivery (BSPDN) is considered essential for CFET to avoid routing congestion.
• Thermal Budget: In monolithic CFET, the bottom device must survive all processing for the top device. In sequential CFET, the bottom device must survive the bonding and top-tier fabrication. Gate stack and junction integrity under extended thermal exposure are critical.

CFET Timeline and Industry Roadmap

Intel's roadmap targets CFET at the Intel 14A node (~2027-2028). Samsung and TSMC are developing CFET for their respective sub-1.4nm nodes. IMEC has demonstrated CFET test structures with functioning stacked N-over-P devices using both monolithic and sequential approaches. The transition from nanosheet to CFET is expected to be the most complex architecture change in CMOS history.

Design Impact

CFET enables standard cell heights of 4-5 tracks (vs. 6-7 tracks for nanosheet), dramatically increasing gate density. However, designers must account for increased parasitic capacitance between stacked devices, thermal coupling between tiers, and the routing complexity of connecting vertically stacked transistors to horizontal metal interconnects.

CFET is the ultimate expression of the semiconductor industry's mantra of vertical scaling — when lateral dimensions can no longer shrink, stack the fundamental building blocks of logic (N and P transistors) on top of each other, converting a 2D layout problem into a 3D integration challenge.