CFET (Complementary FET) is the next-generation transistor architecture that stacks an NMOS transistor directly on top of a PMOS transistor (or vice versa) within the same footprint — effectively halving the standard cell area compared to side-by-side NMOS/PMOS arrangements used in FinFET and nanosheet designs, representing the ultimate density scaling path for logic transistors beyond the 1 nm node.

Why CFET Is Needed

Transistor scaling has progressed: planar → FinFET → Gate-All-Around (GAA) nanosheet. Each transition improved electrostatic control. But even with GAA nanosheets, NMOS and PMOS transistors sit side-by-side in the standard cell, consuming lateral area. At 2 nm, the track height is already ~4.3T — further lateral shrinking creates severe routing congestion and performance degradation. CFET eliminates the lateral NMOS-PMOS boundary entirely.

CFET Architecture

In a conventional CMOS inverter:

• PMOS (left/top) and NMOS (right/bottom) sit side-by-side, sharing a common gate that spans horizontally.
• Cell width = NMOS width + PMOS width + spacing.

In a CFET inverter:

• PMOS nanosheets stacked directly above NMOS nanosheets (or below).
• Common vertical gate wraps around both stacks.
• Cell width = max(NMOS width, PMOS width) — roughly 50% area reduction.

Fabrication Approaches

Monolithic CFET (Sequential Integration): 1. Fabricate bottom device (e.g., NMOS nanosheet) using standard GAA process. 2. Deposit inter-device dielectric isolation layer. 3. Grow or bond epitaxial Si/SiGe layers for top device (PMOS). 4. Fabricate top device (PMOS nanosheet) — limited to low temperatures (<500°C) to avoid degrading the bottom device and its BEOL-like local interconnects. 5. Form vertical contacts connecting top and bottom devices to shared/separate metal layers.

Monolithic CFET is preferred for density but faces severe thermal budget constraints — the top device process cannot exceed temperatures that damage the bottom device.

Sequential CFET (Wafer Bonding): 1. Fabricate NMOS on wafer A and PMOS on wafer B (each with optimized processes). 2. Bond wafer B (flipped) onto wafer A using hybrid bonding. 3. Remove wafer B carrier, exposing PMOS devices aligned to NMOS. 4. Form inter-device contacts.

Sequential CFET allows independent optimization of NMOS and PMOS but requires sub-nm bonding alignment.

Technical Challenges

• Thermal Budget: Bottom device source/drain and contacts must withstand top device processing (~500°C for epitaxy, 400-600°C for activation). Low-temperature epitaxy and laser anneal are critical enablers.
• Contact Routing: Reaching the bottom device's source/drain contacts through the top device layer requires 3D contact schemes with tight pitch and high aspect ratio.
• Power Delivery: CFET's extremely high density exacerbates power delivery challenges — BSPDN is essentially required.
• Design Complexity: New standard cell libraries, EDA tools, and design rules must be developed for vertically stacked logic.

Timeline

• Research demonstrations: imec, IBM, Samsung (2023-2025) showing functional CFET inverters and ring oscillators.
• Expected production: 2028-2030+ for the ~1 nm or Angstrom-class node (A10, 10Å equivalent).

CFET is the 3D transistor architecture that breaks the area scaling wall — achieving the density improvement of an entire process generation through vertical stacking rather than lateral shrinking, representing the final major architectural transformation in CMOS logic scaling before fundamentally new device concepts are needed.