Moore's Law is the observation, first made by Intel co-founder Gordon Moore in 1965 and revised to its familiar form in 1975, that the number of transistors on an integrated circuit doubles roughly every two years. It is not a law of physics but a self-fulfilling industry roadmap — a cadence the whole semiconductor industry organized itself around for half a century, and the engine behind nearly every advance in computing, from the personal computer to the smartphone to modern AI.\n\n``svg\n\n``\n\nThe doubling is exponential, which is why it feels like magic. Intel's 4004 held about 2,300 transistors in 1971; a modern NVIDIA Blackwell GPU holds over 200 billion. That is roughly a hundred-million-fold increase in five decades. On a linear axis the early chips would vanish against today's; on the logarithmic axis above, the whole history collapses onto a nearly straight line, which is the visual signature of steady exponential growth.\n\nDennard scaling was the other half — and it broke first. For decades, shrinking a transistor also lowered the voltage and power it needed, so each generation ran faster at the same power budget. That bonus, called Dennard scaling, ended around 2005. Clock speeds stopped climbing, chips hit a power wall, and the industry pivoted to putting more cores on a die rather than making one core faster — the origin of the multicore era and of "dark silicon," where not all transistors can switch at once.\n\nThe economic version matters as much as the physics. Moore's real claim was about cost: the number of transistors at the lowest cost per transistor doubles on schedule. That framing is why the slowdown hurts. EUV lithography machines cost well over 150 million dollars each, leading-edge fabs run past 20 billion dollars, and mask sets for a new node cost tens of millions — so even when scaling is physically possible, the cost per transistor no longer falls the way it once did.\n\nScaling continued by changing the how, not stopping. Each time one lever ran out, the industry found another: planar transistors gave way to FinFETs around 2011, then to gate-all-around nanosheet devices at the 3 and 2 nm nodes, with backside power delivery, high-NA EUV, 3D stacking, and chiplets extending density gains through packaging rather than pure lithography. This "More than Moore" era keeps effective transistor counts rising even as classic 2D shrink slows.\n\nThe node number is now marketing, not measurement. A "3 nm" process contains no feature that is actually 3 nanometers; the label is a generational name decoupled from physical dimensions. What still tracks Moore's cadence is density — transistors per square millimeter — plus the system-level density that chiplets and stacking add on top.\n\n| Era | Years | Dominant lever | What it bought |\n|---|---|---|---|\n| Planar + Dennard | 1971–2005 | shrink + voltage scaling | speed and density nearly for free |\n| Multicore | 2005–2011 | parallelism | throughput after Dennard broke |\n| FinFET | 2011–2020 | 3D gate control | lower leakage, continued voltage scaling |\n| Gate-all-around | 2022+ | nanosheet electrostatics | density at 3 nm and 2 nm |\n| More than Moore | 2024+ | chiplets, 3D stacking, backside power | system density beyond 2D shrink |\n\nRead Moore's Law through a cost-per-function lens rather than a nanometer lens: what Moore actually predicted was that the cheapest-per-transistor design point would double on a fixed cadence, so the law's health is measured in economics and density, not in the shrinking number on a datasheet. Every era above is a different lever pulled to keep that cadence alive once the previous one ran out — which is why the honest summary is not "Moore's Law is dead" but "the free lunch from simple shrink ended, and scaling now costs more and comes from architecture and packaging as much as from lithography."\n