Semiconductor Economics: Chip, Wafer, and Fab Costs

Overview

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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Chip Economics — Wafer to Packaged Die Cost</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">cost per die = (wafer cost / dies per wafer) / yield — smaller dies and higher yield win</text>

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  <text x="170" y="265" fill="#34d399" font-size="7" text-anchor="middle">good die</text>
  <text x="170" y="278" fill="#f87171" font-size="7" text-anchor="middle">defective (killed by particle)</text>

  <text x="170" y="300" fill="#8b98a5" font-size="8" text-anchor="middle">die size determines yield:</text>
  <text x="170" y="314" fill="#6b7684" font-size="7.5" text-anchor="middle">small die = more per wafer + better yield</text>
  <text x="170" y="328" fill="#6b7684" font-size="7.5" text-anchor="middle">large die = fewer per wafer + yield drops fast</text>

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  <text x="530" y="84" fill="#e6edf3" font-size="10" font-weight="600" text-anchor="middle">Cost per Good Die (3nm example)</text>

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  <text x="355" y="108" fill="#38bdf8" font-size="9.5" font-weight="600">Cost/die = Wafer_cost / (DPW × Y)</text>
  <text x="355" y="126" fill="#8b98a5" font-size="8">DPW = dies per wafer ≈ π×r²/die_area - π×2r/√die_area</text>
  <text x="355" y="142" fill="#8b98a5" font-size="8">Y = (1 + D₀×A/α)^(-α) (negative binomial yield model)</text>

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  <text x="355" y="166" fill="#f59e0b" font-size="9" font-weight="600">H100 die (814 mm²):</text>
  <text x="355" y="182" fill="#8b98a5" font-size="8">wafer=$20K · DPW=60 · yield~50% → $667/die</text>
  <text x="355" y="198" fill="#f59e0b" font-size="9" font-weight="600">A17 Pro (103 mm²):</text>
  <text x="355" y="214" fill="#8b98a5" font-size="8">wafer=$20K · DPW=550 · yield~80% → $45/die</text>

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  <text x="530" y="254" fill="#e6edf3" font-size="10" font-weight="600" text-anchor="middle">Wafer Cost Breakdown (TSMC N3)</text>

  <text x="355" y="274" fill="#6b7684" font-size="7.5">Lithography:</text>
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  <text x="635" y="276" fill="#93c5fd" font-size="7">45% (~$9K)</text>

  <text x="355" y="292" fill="#6b7684" font-size="7.5">Deposition+Etch:</text>
  <rect x="425" y="285" width="100" height="10" rx="2" fill="#34d399" opacity="0.5"/>
  <text x="535" y="294" fill="#6ee7b7" font-size="7">22%</text>

  <text x="355" y="310" fill="#6b7684" font-size="7.5">CMP+Clean:</text>
  <rect x="425" y="303" width="55" height="10" rx="2" fill="#a78bfa" opacity="0.5"/>
  <text x="490" y="312" fill="#c4b5fd" font-size="7">12%</text>

  <text x="355" y="328" fill="#6b7684" font-size="7.5">Ion implant+other:</text>
  <rect x="425" y="321" width="45" height="10" rx="2" fill="#f59e0b" opacity="0.5"/>
  <text x="480" y="330" fill="#fbbf24" font-size="7">10%</text>

  <text x="355" y="342" fill="#6b7684" font-size="7.5">Wafer substrate:</text>
  <rect x="425" y="335" width="22" height="10" rx="2" fill="#f87171" opacity="0.5"/>
  <text x="455" y="344" fill="#fca5a5" font-size="7">$500</text>

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  <text x="380" y="378" fill="#e6edf3" font-size="10" font-weight="600" text-anchor="middle">Economics at Scale</text>
  <text x="50" y="398" fill="#8b98a5" font-size="8.5">• Node shrink: +40% wafer cost, but 2× density → cost/transistor still drops ~25%</text>
  <text x="50" y="414" fill="#8b98a5" font-size="8.5">• Chiplets: slice large die into smaller yield-friendly tiles, reassemble in package</text>

  <text x="380" y="452" fill="#6b7684" font-size="11" text-anchor="middle">Die area × defect density = yield — this single equation drives $100B of semiconductor design decisions.</text>
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Semiconductor economics operates across three interconnected cost levels, each driving the next in a hierarchical structure that determines the final price of every chip.

1. Fab (Fabrication Plant) Cost

The foundation of semiconductor economics—the capital expenditure required to build and equip a fabrication facility.

Capital Expenditure Breakdown

• Modern leading-edge fabs (3nm/2nm): $15–25+ billion to construct
• Historical comparison:
• Year 2000: ~$1–2 billion per fab
• Year 2010: ~$3–5 billion per fab
• Year 2020: ~$10–15 billion per fab
• Year 2024+: ~$20–30 billion per fab

Cost Components

• Equipment (70–80% of capital cost):
• ASML EUV lithography machines: ~$350–400 million each
• Deposition tools (CVD, PVD): $5–20 million each
• Etching systems: $5–15 million each
• Metrology and inspection: $2–10 million each
• Ion implantation: $3–8 million each

• Facility construction (20–30% of capital cost):
• Cleanroom (Class 1-10): $3,000–5,000 per square foot
• Ultra-pure water systems: $100–500 million
• Vibration isolation foundations
• Chemical delivery systems
• HVAC and air filtration

Depreciation Model

Fab equipment is typically depreciated over 5–7 years:

$$ \text{Annual Depreciation} = \frac{\text{Fab Capital Cost}}{\text{Depreciation Period}} $$

Example:

$$ \text{Annual Depreciation} = \frac{\$20 \text{ billion}}{5 \text{ years}} = \$4 \text{ billion/year} $$

2. Wafer Cost

The cost to process a single silicon wafer (typically 300mm diameter) through hundreds of manufacturing steps.

Wafer Cost by Process Node

Wafer Cost Formula

$$ C_{\text{wafer}} = C_{\text{depreciation}} + C_{\text{materials}} + C_{\text{labor}} + C_{\text{utilities}} + C_{\text{overhead}} $$

Where:

• $C_{\text{depreciation}}$ = Equipment depreciation per wafer
• $C_{\text{materials}}$ = Silicon, photoresists, gases, chemicals, CMP slurries
• $C_{\text{labor}}$ = Engineering and technician costs
• $C_{\text{utilities}}$ = Electricity, ultra-pure water, gases
• $C_{\text{overhead}}$ = Maintenance, yield engineering, facility costs

Wafer Throughput Economics

$$ C_{\text{depreciation/wafer}} = \frac{\text{Annual Depreciation}}{\text{Wafers per Year}} $$

Example for a $20B fab producing 100,000 wafers/month:

$$ C_{\text{depreciation/wafer}} = \frac{\$4 \text{ billion/year}}{1.2 \text{ million wafers/year}} \approx \$3,333 \text{ per wafer} $$

3. Chip (Die) Cost

The cost per individual chip, derived from wafer economics and manufacturing yield.

Fundamental Die Cost Equation

$$ C_{\text{die}} = \frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y} $$

Where:

• $C_{\text{die}}$ = Cost per good die
• $C_{\text{wafer}}$ = Total wafer processing cost
• $N_{\text{dies}}$ = Number of dies per wafer (gross)
• $Y$ = Yield (fraction of functional dies)

Dies Per Wafer Calculation

For a circular wafer with rectangular dies:

$$ N_{\text{dies}} \approx \frac{\pi \times D^2}{4 \times A_{\text{die}}} - \frac{\pi \times D}{\sqrt{2 \times A_{\text{die}}}} $$

Where:

• $D$ = Wafer diameter (300mm for modern fabs)
• $A_{\text{die}}$ = Die area in mm²

Simplified approximation:

$$ N_{\text{dies}} \approx \frac{\pi \times (150)^2}{A_{\text{die}}} \times 0.85 $$

The 0.85 factor accounts for edge losses and scribe lines.

Dies Per Wafer Examples

Yield Models

Murphy's Yield Model

$$ Y = \left( \frac{1 - e^{-D_0 \times A}}{D_0 \times A} \right)^2 $$

Poisson Yield Model (simpler)

$$ Y = e^{-D_0 \times A} $$

Where:

• $Y$ = Die yield (fraction)
• $D_0$ = Defect density (defects per cm²)
• $A$ = Die area (cm²)

Typical defect densities:

• Mature process: $D_0 \approx 0.05–0.1$ defects/cm²
• New process (early): $D_0 \approx 0.3–0.5$ defects/cm²
• New process (ramping): $D_0 \approx 0.1–0.2$ defects/cm²

Yield Impact Examples

For a 600mm² die ($A = 6$ cm²):

Mature process ($D_0 = 0.1$):

$$ Y = e^{-0.1 \times 6} = e^{-0.6} \approx 0.55 = 55\% $$

Early production ($D_0 = 0.3$):

$$ Y = e^{-0.3 \times 6} = e^{-1.8} \approx 0.17 = 17\% $$

4. Complete Cost Model

Total Manufacturing Cost Per Chip

$$ C_{\text{total}} = C_{\text{die}} + C_{\text{packaging}} + C_{\text{testing}} + C_{\text{design\_amort}} $$

Where:

$$ C_{\text{design\_amort}} = \frac{C_{\text{NRE}}}{\text{Total Units Produced}} $$

• $C_{\text{NRE}}$ = Non-Recurring Engineering costs (design, masks, validation)

NRE Costs by Node

Packaging Costs

• Standard wire bond: $0.10 – $1.00
• Flip chip BGA: $2 – $10
• Advanced fan-out (InFO): $10 – $50
• 2.5D interposer (CoWoS): $100 – $400
• 3D stacking: $200 – $600+

5. Worked Examples

Example 1: AI Accelerator Chip

Parameters:

• Node: TSMC 5nm
• Die size: 600mm²
• Wafer cost: $17,000
• Defect density: $D_0 = 0.12$ /cm²

Calculations:

Dies per wafer:

$$ N_{\text{dies}} = \frac{\pi \times 150^2}{600} \times 0.85 \approx 100 \text{ dies} $$

Yield:

$$ Y = e^{-0.12 \times 6} \approx e^{-0.72} \approx 0.49 = 49\% $$

Die cost:

$$ C_{\text{die}} = \frac{\$17,000}{100 \times 0.49} = \frac{\$17,000}{49} \approx \$347 $$

Total chip cost:

$$ C_{\text{total}} = \$347 + \$250_{\text{(CoWoS)}} + \$30_{\text{(test)}} + \$50_{\text{(design)}} \approx \$677 $$

Example 2: IoT Microcontroller

Parameters:

• Node: 40nm
• Die size: 5mm²
• Wafer cost: $3,000
• Defect density: $D_0 = 0.05$ /cm²

Calculations:

Dies per wafer:

$$ N_{\text{dies}} = \frac{\pi \times 150^2}{5} \times 0.85 \approx 12,000 \text{ dies} $$

Yield:

$$ Y = e^{-0.05 \times 0.05} \approx e^{-0.0025} \approx 0.997 = 99.7\% $$

Die cost:

$$ C_{\text{die}} = \frac{\$3,000}{12,000 \times 0.997} \approx \$0.25 $$

Total chip cost:

$$ C_{\text{total}} = \$0.25 + \$0.15_{\text{(pkg)}} + \$0.05_{\text{(test)}} + \$0.05_{\text{(design)}} \approx \$0.50 $$

6. Economic Dynamics

Learning Curve Effect

Manufacturing cost decreases with cumulative volume:

$$ C_n = C_1 \times n^{-b} $$

Where:

• $C_n$ = Cost at cumulative unit $n$
• $C_1$ = Cost of first unit
• $b$ = Learning exponent (typically 0.1–0.3 for semiconductors)
• Learning rate = $2^{-b}$ (typically 85–95%)

Economies of Scale

Fab utilization impact:

$$ C_{\text{wafer}}(\text{util}) = \frac{C_{\text{fixed}}}{\text{util}} + C_{\text{variable}} $$

• At 50% utilization: costs ~1.5× baseline
• At 90% utilization: costs ~1.05× baseline
• At 100% utilization: minimum cost achieved

Cost Sensitivity Analysis

Die cost sensitivity to yield:

$$ \frac{\partial C_{\text{die}}}{\partial Y} = -\frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y^2} $$

For large, expensive dies, yield improvements have dramatic cost impacts.

7. Industry Structure Implications

Why Only 3 Companies at Leading Edge

Minimum efficient scale calculation:

$$ \text{Revenue Required} = \frac{\text{Annual CapEx} + \text{R\&D}}{\text{Margin}} $$

$$ \text{Revenue Required} \approx \frac{\$15B + \$5B}{0.40} = \$50B+ \text{ annually} $$

Only TSMC, Samsung, and Intel can sustain this investment level.

Foundry Model Economics

Fabless company advantage:

$$ \text{ROI}_{\text{fabless}} = \frac{\text{Chip Revenue} - \text{Foundry Cost} - \text{Design Cost}}{\text{Design Cost}} $$

IDM (Integrated Device Manufacturer):

$$ \text{ROI}_{\text{IDM}} = \frac{\text{Chip Revenue} - \text{Mfg Cost} - \text{Design Cost}}{\text{Fab CapEx} + \text{Design Cost}} $$

The fabless model eliminates fab capital from the denominator, enabling higher ROI for design-focused companies.

8. Summary Equations

Core Formulas Reference

9. Current Market Dynamics (2024–2025)

Key Trends

• AI demand: Consuming 20%+ of advanced node capacity
• Geopolitical reshoring: Adding 20–30% cost premium for non-Taiwan fabs
• EUV bottleneck: ASML's monopoly constrains expansion
• Advanced packaging: Becoming equal cost driver to node shrinks
• Chiplet economics: Enabling yield improvement through smaller dies

Government Subsidies Impact

• US CHIPS Act: $52B in subsidies
• EU Chips Act: €43B in public/private investment
• Effect: Artificially reducing effective CapEx for new fabs

Document generated: January 2025 Data sources: Industry reports, foundry pricing estimates, public financial disclosures