Tapeout Signoff is the comprehensive verification process completed before submitting chip layout data (GDS/OASIS) to the foundry for mask making — the final gate that ensures the chip is functionally correct, physically clean, and manufacturable.

What Is Tapeout?

• "Tapeout" name: From the era when layout data was submitted on magnetic tape.
• Modern: GDS2 or OASIS file containing all mask layers submitted to foundry via secure server.
• Wafers manufactured 12–16 weeks after tapeout.
• Errors discovered after tapeout → metal ECO spin (expensive) or full respin.

Tapeout Signoff Checklist

Physical Verification:

• DRC (Design Rule Check): 0 violations on all layers (Mentor Calibre, Synopsys IC Validator).
• LVS (Layout vs. Schematic): Layout matches schematic 100%.
• ERC (Electrical Rule Check): Floating nodes, antenna violations = 0.
• Density: Metal density per layer within foundry spec.
• Fill: All layers have required dummy fill inserted.

Timing Signoff:

• STA: WNS ≥ 0, TNS = 0 at all PVT corners (SS, TT, FF) and all modes.
• OCV/AOCV applied, SI effects (crosstalk) included.
• Hold timing clean at all corners.

Power and Reliability:

• IR drop: < 5–10% of VDD at worst case.
• EM: All wires within current density limits for 10-year life.
• EMIR report approved by power team.

Functional Verification:

• Formal equivalence: Post-layout netlist matches pre-layout.
• GLS (Gate-Level Simulation): Key test cases pass with back-annotated delays.
• DFT: Scan chain connectivity verified, ATPG fault coverage target met.

Documentation:

• GDS hierarchy verified: All cells resolved, no missing references.
• Technology file version confirmed with foundry.
• IP licensing: All third-party IP blocks cleared for tapeout.
• Export compliance: EAR99 or applicable export control documentation.

Post-Tapeout Immediate Actions

• Archive full database: GDS, DEF, timing databases, sim databases.
• Freeze design: No changes after tapeout (unless wafers not yet started).
• Begin test program development: ATE programming starts.

Tapeout signoff is the culmination of months or years of engineering work — every checklist item represents a potential failure mode that has been systematically eliminated, and the rigor of the signoff process directly determines first-silicon success probability.