Thermal Design and Analysis for Chips is the multidisciplinary engineering practice that predicts, monitors, and manages on-die temperature distribution — where localized power densities exceeding 100 W/mm² in high-performance processors create thermal hotspots that degrade reliability (electromigration lifetime halves per 10°C increase), cause frequency throttling, and can trigger thermal runaway if the cooling solution cannot dissipate the generated heat.

Thermal Challenge in Modern Chips

Total chip power has plateaued at 200-400W (constrained by cooling), but die area has also shrunk. The result: average power density has increased 3-5x per generation. Worse, power is not uniform — ALU clusters, cache banks, and I/O interfaces create hotspots 2-5x above average power density. A 5nm server CPU may have average power density of 0.5 W/mm² but localized hotspots at 2-3 W/mm².

Thermal Analysis Flow

1. Power Map Generation: After place-and-route, extract switching activity from gate-level simulation and generate a spatial power density map (power per unit area, typically on a 10-100 μm grid). 2. Thermal Model: A 3D finite-element thermal model includes the die (silicon thermal conductivity 148 W/m·K), TIM (thermal interface material, 3-8 W/m·K), heat spreader (copper, 400 W/m·K), and heat sink. Each layer is discretized into thermal RC network elements. 3. Steady-State Simulation: Solve for temperature distribution given constant power and ambient temperature. Identifies worst-case hotspot locations and temperatures. 4. Transient Simulation: Captures thermal response to workload transitions (idle→burst). Silicon's thermal time constant (~1-10 ms for die thickness) creates temperature spikes during bursty workloads that steady-state analysis misses.

On-Die Temperature Monitoring

• BJT Thermal Sensors: Diode-connected transistors whose forward voltage is proportional to absolute temperature (PTAT). Accuracy ±1-3°C after calibration. Scattered across the die (8-32 sensors per chip).
• Ring Oscillator Sensors: Frequency varies with temperature. Digital output, easy to integrate, but accuracy limited to ±5°C.
• Thermal Throttling: When any sensor exceeds the thermal limit (Tj_max, typically 100-125°C), the power management unit reduces clock frequency and/or voltage to limit power dissipation. PROCHOT# signal on Intel CPUs indicates active throttling.

Thermal-Aware Design Techniques

• Activity Spreading: Place high-activity blocks (ALUs, clock buffers) apart from each other, distributing heat across the die.
• Dark Silicon: At a given thermal budget, not all transistors can switch simultaneously. Microarchitectural scheduling selectively activates regions to stay within thermal limits.
• Chiplet Architecture: Distributing compute across multiple smaller dies (chiplets) in a package reduces peak power density and provides more surface area for cooling.

Thermal Design is the physical limit that constrains every modern chip's maximum performance — because a chip that cannot be cooled cannot run at its intended frequency, making thermal analysis and management as fundamental to chip design as logic synthesis and timing closure.