Chiplet Architecture and Disaggregation is the semiconductor design paradigm that decomposes a monolithic system-on-chip into multiple smaller, specialized dies (chiplets) connected through high-bandwidth packaging technologies — enabling each chiplet to be manufactured at its optimal process node, improving yield through smaller die sizes, allowing mix-and-match product configurations, and breaking the reticle size limit that caps monolithic die area at ~800 mm².

Why Chiplets

Monolithic SoC scaling faces fundamental limits:

• Yield: Die yield drops exponentially with area (Poisson model). At D₀=0.1/cm²: 100 mm² die = 90% yield; 800 mm² = 45% yield. Splitting into 4×200 mm² chiplets: each at 82% yield, overall 82%⁴ × assembly yield ≈ 40-45% — BUT each chiplet is independently testable (Known Good Die), so defective chiplets are discarded before assembly, achieving effective system yield >80%.
• Reticle Limit: Maximum die size is limited by scanner field size (~26×33 mm = ~858 mm²). Chiplets bypass this — the assembled package can be 2000+ mm².
• Process Optimization: CPU cores benefit from leading-edge logic (3 nm). I/O and SerDes work fine at 5-7 nm. Analog stays at 12-16 nm. Chiplets let each function use its optimal node.
• Product Flexibility: Assemble different chiplet combinations for different SKUs (4-core laptop vs. 64-core server) from the same chiplet pool.

Industry Implementations

• AMD EPYC (Zen 2/3/4): 8-12 compute chiplets (CCDs) + I/O die. Each CCD: 8 cores manufactured at leading-edge node (TSMC 5 nm for Zen 4). I/O die: memory controllers, PCIe, at 6 nm. Connected via Infinity Fabric on organic substrate.
• AMD MI300X: 8 compute chiplets (XCDs, CDNA 3) + 4 I/O dies (XIDs) + 8 HBM3 stacks on CoWoS-like 2.5D interposer. Total: 153B transistors across 12 chiplets.
• Intel Meteor Lake: 4-tile architecture — compute tile (Intel 4), SoC tile (TSMC N6), GPU tile (TSMC N5), I/O tile (TSMC N6) connected via Foveros 3D stacking + EMIB bridges.
• Apple M-series (Ultra): Two M2 Max dies connected via UltraFusion bridge (~2.5 TB/s bandwidth) creating a single M2 Ultra processor.

Chiplet Interconnect Standards

• UCIe (Universal Chiplet Interconnect Express): Industry-standard die-to-die interface. Physical layer defines bump pitch (25-55 μm for standard packaging, <10 μm for advanced packaging), protocol layer supports PCIe and CXL. Enables chiplets from different vendors to interoperate.
• BoW (Bunch of Wires): Simpler, lower-latency die-to-die link without complex protocol overhead. Used in some AMD designs.
• Proprietary: AMD Infinity Fabric, Intel EMIB/Foveros AIB, TSMC LIPINCON.

Design Challenges

• Die-to-Die Bandwidth: Cross-chiplet communication must approach the bandwidth of intra-die wires. UCIe advanced package: 1.3 TB/s per mm edge × 2 edges = multi-TB/s per chiplet pair. Standard package: lower bandwidth, higher latency.
• Latency: Cross-chiplet latency (10-50 ns vs. <1 ns intra-die) impacts cache coherency performance. NUMA-like effects between chiplets require software awareness.
• Power: Die-to-die I/O power: 0.2-0.5 pJ/bit for advanced packaging, 2-5 pJ/bit for standard packaging. At TB/s bandwidths, this is a significant power budget item.
• Known Good Die (KGD): Each chiplet must be fully tested before assembly. Defective chiplets discovered after bonding waste the entire package.

Chiplet Architecture is the semiconductor industry's answer to the practicality limits of monolithic scaling — a disaggregation strategy that achieves the performance, density, and functionality of impossibly large monolithic dies by composing smaller, optimized, independently manufactured chiplets into unified systems.