Chiplet Interconnect Standards and Architecture encompasses the physical interface, protocol, and packaging technologies that enable multiple semiconductor dies (chiplets) to communicate within a single package — with UCIe (Universal Chiplet Interconnect Express) emerging as the industry standard for die-to-die communication, defining electrical specifications, protocol layers, and packaging requirements to enable a plug-and-play chiplet ecosystem.

Why Chiplet Interconnects Matter:

The chiplet model disaggregates monolithic SoCs into smaller, specialized dies (compute, I/O, memory, accelerator) that are assembled in a package. This requires die-to-die (D2D) links that are:

• High bandwidth: >1 TB/s aggregate for AI accelerators
• Low latency: <2ns for cache-coherent communication
• Energy efficient: <0.5 pJ/bit (100× better than off-package links)
• Standardized: Enable mixing chiplets from different vendors/processes

UCIe (Universal Chiplet Interconnect Express):

UCIe 1.0 (2022) and UCIe 2.0 (2024) define a layered architecture:

<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">UCIe: an open, PCIe-like standard for die-to-die links</text><text x="20" y="50" fill="#8b949e" font-size="12.5">A layered stack over standard or advanced packages lets chiplets from any vendor or node snap together in one package</text><!-- ===== PANEL 1: layered like PCIe ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#38bdf8" font-size="12" font-weight="700">1 &#183; Layered like PCIe</text><rect x="32" y="120" width="40" height="76" fill="#38506a" stroke="#6f8fb0"/><text x="52" y="161" fill="#dbe7f3" font-size="8.5" text-anchor="middle" transform="rotate(-90 52 161)">Die A</text><rect x="194" y="120" width="40" height="76" fill="#6b5fb0" stroke="#8f83c9"/><text x="214" y="161" fill="#e9e3ff" font-size="8.5" text-anchor="middle" transform="rotate(-90 214 161)">Die B</text><rect x="78" y="120" width="110" height="23" fill="#122b22" stroke="#3f9d6f"/><text x="133" y="131" fill="#7ee6c0" font-size="8" text-anchor="middle" font-weight="700">Protocol layer</text><text x="133" y="140" fill="#adb5bd" font-size="6.8" text-anchor="middle">PCIe / CXL / raw streaming</text><rect x="78" y="144" width="110" height="23" fill="#2e2617" stroke="#e0b13a"/><text x="133" y="155" fill="#e0b13a" font-size="8" text-anchor="middle" font-weight="700">Die-to-die adapter</text><text x="133" y="164" fill="#adb5bd" font-size="6.8" text-anchor="middle">link state &#183; CRC &#183; retry &#183; arbitration</text><rect x="78" y="168" width="110" height="23" fill="#10263a" stroke="#38bdf8"/><text x="133" y="179" fill="#38bdf8" font-size="8" text-anchor="middle" font-weight="700">Physical layer</text><text x="133" y="188" fill="#adb5bd" font-size="6.8" text-anchor="middle">bumps &#183; lanes &#183; clock &#183; sideband</text><g fill="#e0b13a"><circle cx="88" cy="197" r="2"/><circle cx="100" cy="197" r="2"/><circle cx="112" cy="197" r="2"/><circle cx="124" cy="197" r="2"/><circle cx="136" cy="197" r="2"/><circle cx="148" cy="197" r="2"/><circle cx="160" cy="197" r="2"/><circle cx="172" cy="197" r="2"/></g><text x="32" y="222" fill="#adb5bd" font-size="8.6">UCIe stacks like PCIe: a physical layer,</text><text x="32" y="234" fill="#adb5bd" font-size="8.6">a die-to-die adapter, and a protocol layer</text><text x="32" y="246" fill="#adb5bd" font-size="8.6">that just carries PCIe, CXL, or raw streams.</text><text x="32" y="268" fill="#38bdf8" font-size="8.6" font-weight="600">Existing software works across the die edge.</text><text x="32" y="290" fill="#8b949e" font-size="8.4">A sideband channel trains and repairs</text><text x="32" y="302" fill="#8b949e" font-size="8.4">lanes; CRC + retry keep the link reliable.</text><text x="32" y="324" fill="#8b949e" font-size="8.4">Buy an I/O die from one vendor, a compute</text><text x="32" y="336" fill="#8b949e" font-size="8.4">die from another &#8212; they interoperate.</text><!-- ===== PANEL 2: pick your package ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#a99cf0" font-size="12" font-weight="700">2 &#183; Pick your package</text><text x="380" y="106" fill="#dbe7f3" font-size="8.3" text-anchor="middle" font-weight="700">standard package (organic)</text><rect x="298" y="114" width="42" height="16" fill="#38506a" stroke="#6f8fb0"/><rect x="420" y="114" width="42" height="16" fill="#6b5fb0" stroke="#8f83c9"/><rect x="290" y="132" width="182" height="9" fill="#5a4632" stroke="#6f6f6a"/><g fill="#c98a2e"><circle cx="308" cy="131" r="2.4"/><circle cx="322" cy="131" r="2.4"/><circle cx="334" cy="131" r="2.4"/><circle cx="428" cy="131" r="2.4"/><circle cx="442" cy="131" r="2.4"/><circle cx="454" cy="131" r="2.4"/></g><line x1="342" y1="122" x2="418" y2="122" stroke="#8b949e" stroke-width="0.7" stroke-dasharray="3 2"/><text x="380" y="120" fill="#8b949e" font-size="6.6" text-anchor="middle">reach 10&#8211;25 mm</text><text x="380" y="154" fill="#adb5bd" font-size="7.6" text-anchor="middle">coarse pitch &#183; lower density &#183; cheaper</text><text x="380" y="176" fill="#dbe7f3" font-size="8.3" text-anchor="middle" font-weight="700">advanced package (2.5D interposer)</text><rect x="330" y="184" width="44" height="16" fill="#38506a" stroke="#6f8fb0"/><rect x="388" y="184" width="44" height="16" fill="#6b5fb0" stroke="#8f83c9"/><text x="381" y="182" fill="#8b949e" font-size="6.6" text-anchor="middle">~2 mm</text><rect x="312" y="202" width="148" height="9" fill="#2b2f36" stroke="#6f6f6a"/><g fill="#b8732e"><circle cx="338" cy="201" r="1.3"/><circle cx="346" cy="201" r="1.3"/><circle cx="354" cy="201" r="1.3"/><circle cx="362" cy="201" r="1.3"/><circle cx="370" cy="201" r="1.3"/><circle cx="378" cy="201" r="1.3"/><circle cx="386" cy="201" r="1.3"/><circle cx="394" cy="201" r="1.3"/><circle cx="402" cy="201" r="1.3"/><circle cx="410" cy="201" r="1.3"/><circle cx="418" cy="201" r="1.3"/><circle cx="426" cy="201" r="1.3"/></g><text x="380" y="224" fill="#7ee6c0" font-size="7.6" text-anchor="middle">fine pitch &#183; high density &#183; sub-0.5 pJ/bit</text><line x1="279" y1="236" x2="481" y2="236" stroke="#30363d" stroke-width="1"/><text x="279" y="256" fill="#adb5bd" font-size="8.6">The same UCIe stack runs on both. You</text><text x="279" y="268" fill="#adb5bd" font-size="8.6">pick the package for your cost-versus-</text><text x="279" y="280" fill="#adb5bd" font-size="8.6">bandwidth target.</text><text x="279" y="302" fill="#a99cf0" font-size="8.6" font-weight="600">Reach trades against bandwidth density.</text><!-- ===== PANEL 3: what it's really for ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#34d399" font-size="12" font-weight="700">3 &#183; What it's really for</text><text x="526" y="108" fill="#e6edf3" font-size="10" font-weight="700">Figures of merit</text><text x="526" y="126" fill="#adb5bd" font-size="8.7">&#8226; bandwidth per mm of die edge</text><text x="526" y="142" fill="#adb5bd" font-size="8.7">&#8226; energy per bit (adv: &#60;0.5 pJ/bit)</text><text x="526" y="158" fill="#adb5bd" font-size="8.7">&#8226; die-to-die latency &#60; ~2 ns</text><text x="526" y="176" fill="#8b949e" font-size="8">Not raw speed &#8212; edge is scarce, so it's</text><text x="526" y="188" fill="#8b949e" font-size="8">bandwidth and energy per bit that count.</text><line x1="526" y1="200" x2="728" y2="200" stroke="#30363d" stroke-width="1"/><text x="526" y="219" fill="#34d399" font-size="10" font-weight="700">Ends the proprietary links</text><text x="526" y="237" fill="#adb5bd" font-size="8.6">Infinity Fabric, EMIB/AIB and NVLink-C2C</text><text x="526" y="249" fill="#adb5bd" font-size="8.6">each stitch one vendor's dies. UCIe is</text><text x="526" y="261" fill="#adb5bd" font-size="8.6">open, so dies from different vendors and</text><text x="526" y="273" fill="#adb5bd" font-size="8.6">process nodes mix in one package.</text><text x="526" y="295" fill="#34d399" font-size="8.6" font-weight="600">&#8594; a marketplace of composable dies.</text><text x="526" y="315" fill="#8b949e" font-size="8.3">Crossing a die edge feels almost on-die.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="404" fill="#38bdf8" font-size="10.5" font-weight="700">Layered like PCIe</text><text x="32" y="421" fill="#adb5bd" font-size="8.7">Physical layer, D2D adapter, protocol</text><text x="32" y="434" fill="#adb5bd" font-size="8.7">layer &#8212; and the top reuses PCIe/CXL, so</text><text x="32" y="447" fill="#adb5bd" font-size="8.7">software crosses the die edge unchanged.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="404" fill="#a99cf0" font-size="10.5" font-weight="700">Two package classes</text><text x="279" y="421" fill="#adb5bd" font-size="8.7">Standard organic for reach and low cost;</text><text x="279" y="434" fill="#adb5bd" font-size="8.7">advanced 2.5D for density and pJ/bit &#8212;</text><text x="279" y="447" fill="#adb5bd" font-size="8.7">one stack, two cost/bandwidth points.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="404" fill="#34d399" font-size="10.5" font-weight="700">Open beats proprietary</text><text x="526" y="421" fill="#adb5bd" font-size="8.7">One standard link turns chiplets from a</text><text x="526" y="434" fill="#adb5bd" font-size="8.7">one-vendor trick into an ecosystem of</text><text x="526" y="447" fill="#adb5bd" font-size="8.7">mix-and-match, composable dies.</text></svg>

UCIe Physical Layer Options:

Advanced packaging with 25μm bump pitch provides ~6× the bandwidth density of standard packaging.

Protocol Options:

• PCIe streaming: For standard I/O communication (NIC chiplets, storage controllers)
• CXL: For cache-coherent memory expansion and memory pooling chiplets
• Custom/Raw: Proprietary protocols for vendor-specific high-bandwidth communication (e.g., AMD's Infinity Fabric, Intel's EMIB-connected tiles)

Existing Proprietary D2D Links:

Signal Integrity Challenges:

D2D links at 16-32 GT/s across microbumps face: crosstalk between closely spaced signals (~25μm pitch), power supply noise coupling through shared substrate, impedance discontinuities at bump transitions, and thermal effects on signal propagation. Solutions include: shielding ground lines between signal lanes, equalization (CTLE + limited DFE), and careful power distribution network design on the interposer.

Chiplet interconnect standardization through UCIe is the technical foundation enabling a heterogeneous chiplet ecosystem — allowing the semiconductor industry to transition from monolithic SoC design to a modular, multi-vendor chiplet assembly paradigm where compute, memory, I/O, and accelerator dies from different companies and process nodes can be combined in a single package.