Chiplet Technology — a modular chip architecture where a single package contains multiple smaller dies (chiplets) connected by high-bandwidth interconnects, replacing the traditional monolithic die approach.

Why Chiplets?

• Monolithic die at 3nm: Yield drops exponentially with die size (a 600mm² die at 3nm might have <30% yield)
• Chiplets: Split into smaller dies with much higher yield, then assemble
• Mix process nodes: Compute chiplet at 3nm, I/O chiplet at cheaper 7nm
• IP reuse: Same chiplet design used across product families

Interconnect Technologies

• EMIB (Intel): Silicon bridge embedded in package substrate. Connects adjacent chiplets
• CoWoS (TSMC): Silicon interposer connecting multiple chiplets. Used in NVIDIA H100/H200
• UCIe (Universal Chiplet Interconnect Express): Industry standard chiplet interface (like PCIe for chiplets)
• Hybrid Bonding: Direct Cu-Cu connection between stacked dies. Highest bandwidth density

Real Products

• AMD EPYC: Up to 12 CCD chiplets + 1 IOD (I/O die)
• AMD MI300X: 8 XCD + 4 HBM stacks on CoWoS
• Apple M2 Ultra: Two M2 Max dies connected by UltraFusion
• Intel Meteor Lake: Compute + GPU + SoC + I/O chiplets in Foveros package

Chiplet technology is the industry's answer to the end of easy monolithic scaling — it delivers more transistors per package by assembling multiple optimized dies.