Chiplet Technology is the design approach of building a system from multiple smaller, specialized silicon dies (chiplets) interconnected in a single package — replacing monolithic large dies with composable building blocks that can be manufactured at different process nodes, tested independently, and mixed-and-matched to create diverse products, dramatically improving yield, reducing cost, and accelerating time-to-market.
Why Chiplets?
- Yield: A 800mm² monolithic die at D₀=0.1 → ~45% yield. Four 200mm² chiplets → ~82% yield each → 45% vs. $0.82^4$ = 45% but each chiplet is individually tested → defective ones discarded cheaply.
- Cost: Not all functions need leading-edge process. CPU cores at 3nm, I/O at 7nm, SRAM at 5nm → optimize cost per function.
- Reuse: Same CPU chiplet used across desktop, server, and mobile products with different configurations.
- Time-to-market: Design smaller chiplets faster → assemble into products.
Chiplet Interconnect Technologies
| Technology | Pitch | Bandwidth Density | Die-to-Die |
|---|---|---|---|
| Standard package (organic) | 100-200 μm | 2-10 GB/s/mm | Via substrate |
| EMIB (Intel) | 45-55 μm | 20-50 GB/s/mm | Embedded bridge |
| CoWoS (TSMC) | 40-45 μm | 20-40 GB/s/mm | Silicon interposer |
| SoIC (TSMC) | 5-10 μm | 100+ GB/s/mm | Direct bonding (3D) |
| Foveros (Intel) | 25-36 μm | 50-100 GB/s/mm | Face-to-face 3D |
| UCIe (standard) | 25-55 μm | 28-224 GB/s | Standardized interface |
UCIe (Universal Chiplet Interconnect Express)
- Industry standard (Intel, AMD, ARM, TSMC, Samsung, ASE, and others).
- Defines: Physical layer, protocol layer, and software stack for die-to-die communication.
- Supports: Standard package (bump pitch ~100 μm) and advanced package (~25 μm).
- Bandwidth: 28 GB/s (standard) to 224 GB/s (advanced) per mm of edge.
- Goal: Mix chiplets from different vendors — like PCIe for die-to-die interconnect.
Industry Examples
| Product | Chiplet Architecture | Process Mix |
|---|---|---|
| AMD EPYC (Genoa) | 12 CCD + 1 IOD | CCD: 5nm, IOD: 6nm |
| AMD MI300X | 8 XCD + 4 IOD | XCD: 5nm, IOD: 6nm |
| Intel Meteor Lake | CPU + GPU + SoC + I/O tiles | CPU: Intel 4, SoC: TSMC N6 |
| Apple M2 Ultra | 2× M2 Max connected | TSMC N5, UltraFusion bridge |
| NVIDIA Grace Hopper | CPU + GPU chiplets | TSMC 4N |
Chiplet Challenges
- Known Good Die (KGD): Must test chiplets before assembly — defective chiplet wastes entire package.
- Thermal management: Multiple heat sources in one package — complex thermal solution.
- Interconnect latency: Die-to-die communication adds 2-10 ns vs. on-die wires.
- Power delivery: Each chiplet needs adequate power supply through shared substrate.
Chiplet technology is the most important packaging innovation of the decade — by decoupling silicon design from monolithic die constraints, chiplets enable the continuation of system-level performance scaling even as single-die scaling faces diminishing returns from Moore's Law.
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