Clock gating disables the clock signal to idle logic blocks to reduce dynamic power consumption, which is the most widely used and effective power reduction technique in digital IC design. Principle: dynamic power P = αCV²f—if clock is gated (f=0 for that block), switching activity α drops to zero, eliminating dynamic power. Implementation: (1) Latch-based clock gating—AND gate with enable latch prevents glitches on gated clock; (2) Integrated clock gating (ICG) cell—standard cell with built-in latch, enable, and AND gate; (3) Library ICG—foundry-provided cells optimized for area and timing. Clock gating levels: (1) RTL-level—designer inserts explicit clock enables in HDL; (2) Synthesis-level—tool automatically infers clock gating from register enable conditions; (3) Architectural—power management unit controls clock domains. Effectiveness: typically saves 20-40% dynamic power in a design. Multi-level clock gating: (1) Fine-grain—individual register groups; (2) Module-level—functional unit clock disable; (3) Top-level—entire clock domain shutdown. Clock gating vs. data gating: clock gating stops clock toggles, data gating holds data stable (both reduce power but clock gating more effective). Verification: functional equivalence (gated vs. ungated), clock domain crossing analysis, timing analysis of gating paths. Timing considerations: ICG enable setup/hold relative to clock edge, clock gating penalty (additional clock latency). Physical design: ICG cells placed near clock tree insertion points. Implementation in modern SoCs: thousands of ICG cells, automated by synthesis tools, verified by power analysis. Most power-efficient technique available—virtually every production digital design uses clock gating extensively.