Clock Gating — disabling the clock signal to registers that don't need to update, preventing useless toggling and reducing dynamic power by 20–60%.

The Problem

• Clock network is the #1 power consumer in a digital chip (30–50% of total dynamic power)
• Every register's clock input toggles every cycle, even if the register's data hasn't changed
• Wasted switching = wasted power

How Clock Gating Works

<svg viewBox="0 0 351 112" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="351" height="112" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">Original:  clk </tspan><tspan fill="#6e7681">───────────────</tspan><tspan fill="#c9d1d9"> FF.clk</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">Gated:     clk </tspan><tspan fill="#6e7681">──┐</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#c9d1d9">                  AND </tspan><tspan fill="#6e7681">────────</tspan><tspan fill="#c9d1d9"> FF.clk</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#c9d1d9">           EN </tspan><tspan fill="#6e7681">───┘</tspan></text></g></svg>

• When EN=0: Clock is blocked → flip-flop doesn't toggle → zero dynamic power
• When EN=1: Clock passes through → normal operation

ICG (Integrated Clock Gating) Cell

• Latch-based clock gate: Avoids glitches by latching the enable signal
• Standard cell libraries include optimized ICG cells
• Synthesis tools automatically insert clock gates (RTL compiler detects when registers share enable conditions)

Levels of Clock Gating

• RTL-level: Designer explicitly gates modules/blocks. Coarsest, most effective
• Synthesis-level: Tool automatically groups registers with same enable. Fine-grained
• Activity-based: Dynamic analysis identifies low-activity registers for gating

Impact

• Typical savings: 20–40% of total chip power
• Standard in every modern design — no chip ships without clock gating
• EDA tools report clock gating efficiency metrics

Clock gating is the single most impactful power optimization technique in digital design — it's always the first thing to implement.