Clock skew is the timing difference between the arrival of the same clock edge at two different sequential elements (flip-flops, latches) — one of the most critical parameters in synchronous digital design because it directly consumes timing margin and limits maximum clock frequency.
Formal Definition
$$\text{Skew}_{AB} = t_{clk,A} - t_{clk,B}$$
Where $t_{clk,A}$ and $t_{clk,B}$ are the clock arrival times at flip-flops A and B respectively.
- Positive Skew: Clock arrives at the capturing flip-flop later than at the launching flip-flop — helps setup (more time for data to propagate) but hurts hold (data may change too quickly at the receiver).
- Negative Skew: Clock arrives at the capturing flip-flop earlier — hurts setup (less time available) but helps hold.
Impact on Timing
- Setup Constraint: Data must arrive at the capturing FF before the clock edge:
$$T_{period} + \text{Skew}_{launch→capture} \geq t_{CQ} + t_{comb} + t_{setup}$$
Negative skew reduces the available time window.
- Hold Constraint: Data must be stable after the clock edge:
$$t_{CQ} + t_{comb} \geq t_{hold} + \text{Skew}_{launch→capture}$$
Positive skew makes hold harder to meet.
- The Dilemma: Skew that improves setup makes hold worse, and vice versa. The only universally "good" answer is zero skew — or intentionally managed "useful skew."
Sources of Clock Skew
- Wire Length Differences: Different path lengths from clock source to different flip-flops — the primary source, addressed by CTS.
- Buffer Mismatches: Variations in buffer delay due to process variation, voltage, and temperature (PVT).
- Load Imbalance: Different capacitive loads at different clock sinks cause different buffer delays.
- On-Chip Variation (OCV): Within-die process variation causes nominally identical paths to have different delays.
- Routing Asymmetry: Different layers, different via counts, or different coupling environments along different clock paths.
Skew Metrics
- Global Skew: Maximum clock arrival time difference between any two flip-flops in the entire design.
- Local Skew: Clock arrival time difference between two flip-flops connected by a data path (the one that actually matters for timing).
- Intra-Clock Skew: Skew within one clock domain.
- Inter-Clock Skew: Timing relationship between different clock domains — managed by synchronizers, not CTS.
Managing Clock Skew
- CTS (Clock Tree Synthesis): Build balanced buffer trees to minimize skew.
- Clock Mesh: Shorten clock wires to reduce skew through nearest-neighbor averaging.
- Useful Skew: Intentionally introduce skew to improve critical paths (borrow time from slack-rich paths).
- PLL/DLL: Active circuits that lock clock phase and compensate for skew.
Clock skew is the fundamental constraint of synchronous design — managing it to within a few picoseconds is essential for multi-GHz operation.