<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="Segoe UI,Arial,sans-serif"><rect width="760" height="470" fill="#0d1117"/><defs><marker id="ah" markerWidth="8" markerHeight="8" refX="6.5" refY="3" orient="auto"><path d="M0,0 L7,3 L0,6 Z" fill="#8b949e"/></marker><marker id="ad" markerWidth="7" markerHeight="7" refX="3.5" refY="3" orient="auto"><path d="M0,0 L7,3 L0,6 Z" fill="#fbbf24"/></marker><marker id="ade" markerWidth="7" markerHeight="7" refX="3.5" refY="3" orient="auto-start-reverse"><path d="M0,0 L7,3 L0,6 Z" fill="#fbbf24"/></marker></defs><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Clock distribution: one edge to every flip-flop, on time and gated when idle</text><text x="20" y="50" fill="#8b949e" font-size="12.5">A balanced tree delivers the same edge everywhere. Skew and jitter erode timing margin; gating stops idle toggling.</text><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="87" fill="#e6edf3" font-size="13.5" font-weight="600">Balanced H-tree (CTS)</text><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="87" fill="#e6edf3" font-size="13.5" font-weight="600">Skew &amp; jitter</text><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="87" fill="#e6edf3" font-size="13.5" font-weight="600">Clock gating</text><path d="M129,226 L137,230 L129,234 Z" fill="#fbbf24"/><line x1="61" y1="230" x2="205" y2="230" stroke="#60a5fa" stroke-width="1.4"/><path d="M57,226 L65,230 L57,234 Z" fill="#fbbf24"/><line x1="61" y1="194" x2="61" y2="266" stroke="#60a5fa" stroke-width="1.4"/><path d="M57,190 L65,194 L57,198 Z" fill="#fbbf24"/><line x1="43" y1="194" x2="79" y2="194" stroke="#60a5fa" stroke-width="1.4"/><path d="M39,190 L47,194 L39,198 Z" fill="#fbbf24"/><line x1="43" y1="185" x2="43" y2="203" stroke="#60a5fa" stroke-width="1.4"/><rect x="38" y="180" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="38" y="198" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M75,190 L83,194 L75,198 Z" fill="#fbbf24"/><line x1="79" y1="185" x2="79" y2="203" stroke="#60a5fa" stroke-width="1.4"/><rect x="74" y="180" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="74" y="198" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M57,262 L65,266 L57,270 Z" fill="#fbbf24"/><line x1="43" y1="266" x2="79" y2="266" stroke="#60a5fa" stroke-width="1.4"/><path d="M39,262 L47,266 L39,270 Z" fill="#fbbf24"/><line x1="43" y1="257" x2="43" y2="275" stroke="#60a5fa" stroke-width="1.4"/><rect x="38" y="252" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="38" y="270" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M75,262 L83,266 L75,270 Z" fill="#fbbf24"/><line x1="79" y1="257" x2="79" y2="275" stroke="#60a5fa" stroke-width="1.4"/><rect x="74" y="252" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="74" y="270" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M201,226 L209,230 L201,234 Z" fill="#fbbf24"/><line x1="205" y1="194" x2="205" y2="266" stroke="#60a5fa" stroke-width="1.4"/><path d="M201,190 L209,194 L201,198 Z" fill="#fbbf24"/><line x1="187" y1="194" x2="223" y2="194" stroke="#60a5fa" stroke-width="1.4"/><path d="M183,190 L191,194 L183,198 Z" fill="#fbbf24"/><line x1="187" y1="185" x2="187" y2="203" stroke="#60a5fa" stroke-width="1.4"/><rect x="182" y="180" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="182" y="198" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M219,190 L227,194 L219,198 Z" fill="#fbbf24"/><line x1="223" y1="185" x2="223" y2="203" stroke="#60a5fa" stroke-width="1.4"/><rect x="218" y="180" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="218" y="198" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M201,262 L209,266 L201,270 Z" fill="#fbbf24"/><line x1="187" y1="266" x2="223" y2="266" stroke="#60a5fa" stroke-width="1.4"/><path d="M183,262 L191,266 L183,270 Z" fill="#fbbf24"/><line x1="187" y1="257" x2="187" y2="275" stroke="#60a5fa" stroke-width="1.4"/><rect x="182" y="252" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="182" y="270" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><path d="M219,262 L227,266 L219,270 Z" fill="#fbbf24"/><line x1="223" y1="257" x2="223" y2="275" stroke="#60a5fa" stroke-width="1.4"/><rect x="218" y="252" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="218" y="270" width="10" height="10" rx="2" fill="#0c2a30" stroke="#22d3ee" stroke-width="1.1"/><rect x="109" y="217" width="48" height="26" rx="4" fill="#241d33" stroke="#c4b5fd" stroke-width="1.5"/><text x="133" y="234" fill="#e6edf3" font-size="10.5" text-anchor="middle" font-weight="700">PLL</text><path d="M32,102 L40,106 L32,110 Z" fill="#fbbf24"/><text x="46" y="109" fill="#8b949e" font-size="9">buffer</text><rect x="96" y="102" width="9" height="9" rx="2" fill="#0c2a30" stroke="#22d3ee"/><text x="110" y="109" fill="#8b949e" font-size="9">flip-flop</text><text x="133" y="348" fill="#8b949e" font-size="9.3" text-anchor="middle">equal path length → every leaf ticks together</text><text x="279" y="130" fill="#93c5fd" font-size="9.5">clk@A</text><polyline points="331,134 379,134 379,118 473,118" fill="none" stroke="#60a5fa" stroke-width="1.6"/><text x="279" y="174" fill="#f0abfc" font-size="9.5">clk@B</text><polyline points="331,178 401,178 401,162 473,162" fill="none" stroke="#f472b6" stroke-width="1.6"/><line x1="379" y1="110" x2="379" y2="186" stroke="#8b949e" stroke-width="1" stroke-dasharray="3 2"/><text x="379" y="107" fill="#8b949e" font-size="8.5" text-anchor="middle">ideal edge</text><line x1="379" y1="200" x2="401" y2="200" stroke="#fbbf24" stroke-width="1.3" marker-start="url(#ade)" marker-end="url(#ad)"/><text x="390" y="213" fill="#fbbf24" font-size="9" text-anchor="middle">skew Δ</text><text x="279" y="203" fill="#8b949e" font-size="8.7">arrival gap</text><text x="279" y="246" fill="#67e8f9" font-size="9.5">jitter</text><rect x="385" y="228" width="20" height="28" fill="#22d3ee" opacity="0.16"/><polyline points="331,250 395,250 395,234 473,234" fill="none" stroke="#22d3ee" stroke-width="1.6"/><line x1="385" y1="228" x2="385" y2="256" stroke="#22d3ee" stroke-width="0.8" stroke-dasharray="2 2"/><line x1="405" y1="228" x2="405" y2="256" stroke="#22d3ee" stroke-width="0.8" stroke-dasharray="2 2"/><text x="413" y="250" fill="#8b949e" font-size="8.7">edge wanders each cycle</text><text x="279" y="350" fill="#e6edf3" font-size="9.5">both subtract from the setup / hold budget</text><rect x="554" y="114" width="42" height="30" rx="4" fill="#12233a" stroke="#60a5fa" stroke-width="1.3"/><text x="575" y="133" fill="#e6edf3" font-size="9.5" text-anchor="middle" font-weight="600">latch</text><line x1="528" y1="123" x2="554" y2="123" stroke="#34d399" stroke-width="1.4" marker-end="url(#ah)"/><text x="528" y="119" fill="#6ee7b7" font-size="9">EN</text><line x1="528" y1="138" x2="554" y2="138" stroke="#fbbf24" stroke-width="1.4" marker-end="url(#ah)"/><text x="528" y="150" fill="#fbbf24" font-size="9">CLK</text><path d="M624,116 H638 A13 13 0 0 1 638,142 H624 Z" fill="#0f2119" stroke="#34d399" stroke-width="1.4"/><text x="633" y="132" fill="#6ee7b7" font-size="8" text-anchor="middle">&amp;</text><line x1="596" y1="123" x2="624" y2="122" stroke="#8b949e" stroke-width="1.2"/><line x1="596" y1="138" x2="624" y2="136" stroke="#fbbf24" stroke-width="1.2"/><line x1="651" y1="129" x2="682" y2="129" stroke="#22d3ee" stroke-width="1.5" marker-end="url(#ah)"/><text x="666.5" y="125" fill="#67e8f9" font-size="8" text-anchor="middle">GCLK</text><rect x="682" y="114" width="42" height="30" rx="4" fill="#111a24" stroke="#30363d"/><text x="703" y="128" fill="#cdd9e5" font-size="8.5" text-anchor="middle">idle</text><text x="703" y="138" fill="#cdd9e5" font-size="8.5" text-anchor="middle">block</text><text x="526" y="195" fill="#fbbf24" font-size="9">CLK</text><polyline points="558,197 558,184 570,184 570,197 582,197 582,184 594,184 594,197 606,197 606,184 618,184 618,197 630,197 630,184 642,184 642,197 654,197 654,184 666,184 666,197 678,197 678,184 690,184 690,197 702,197 702,184 714,184 714,197 720,197" fill="none" stroke="#fbbf24" stroke-width="1.5"/><text x="526" y="229" fill="#34d399" font-size="9">EN</text><polyline points="558,218 642,218 642,231 720,231" fill="none" stroke="#34d399" stroke-width="1.5"/><text x="526" y="263" fill="#67e8f9" font-size="9">GCLK</text><polyline points="558,265 558,252 570,252 570,265 582,265 582,252 594,252 594,265 606,265 606,252 618,252 618,265 630,265 630,252 642,252 654,265 666,265 678,265 690,265 702,265 714,265 720,265" fill="none" stroke="#22d3ee" stroke-width="1.5"/><rect x="642" y="248" width="78" height="21" fill="#8b949e" opacity="0.12"/><text x="681" y="278" fill="#8b949e" font-size="8.3" text-anchor="middle">clock stopped</text><text x="526" y="350" fill="#e6edf3" font-size="9.4">EN low → no toggling → dynamic power saved</text><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="403" fill="#e6edf3" font-size="12.5" font-weight="700">Tree, mesh, and CTS</text><text x="32" y="420" fill="#cdd9e5" font-size="9.7">Buffers replicate one edge to millions of</text><text x="32" y="432.5" fill="#cdd9e5" font-size="9.7">flops. H-trees and meshes equalize path length</text><text x="32" y="445" fill="#cdd9e5" font-size="9.7">so every leaf ticks together — built by</text><text x="32" y="457.5" fill="#cdd9e5" font-size="9.7">clock tree synthesis.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="403" fill="#e6edf3" font-size="12.5" font-weight="700">Skew &amp; jitter eat margin</text><text x="279" y="420" fill="#cdd9e5" font-size="9.7">Skew is the spatial arrival gap between flops;</text><text x="279" y="432.5" fill="#cdd9e5" font-size="9.7">jitter is cycle-to-cycle edge wander. Both</text><text x="279" y="445" fill="#cdd9e5" font-size="9.7">come straight out of the setup / hold budget.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="403" fill="#e6edf3" font-size="12.5" font-weight="700">Gating saves power</text><text x="526" y="420" fill="#cdd9e5" font-size="9.7">An ICG cell ANDs the clock with an enable so</text><text x="526" y="432.5" fill="#cdd9e5" font-size="9.7">idle blocks stop toggling. The clock net is</text><text x="526" y="445" fill="#cdd9e5" font-size="9.7">the biggest dynamic-power sink, so gating it</text><text x="526" y="457.5" fill="#cdd9e5" font-size="9.7">wins most.</text></svg>

Clock Tree Synthesis (CTS) is the automated physical design process of building a balanced, optimized clock distribution network that delivers the clock signal from its source to every sequential element (flip-flop, register, latch) in the design — with minimal skew, controlled insertion delay, acceptable transition times, and low power consumption.

Why CTS Is Critical

• A modern SoC can have millions of flip-flops — all needing a clean, well-timed clock.
• The clock is the highest switching-activity net on the chip — it toggles every cycle at every flip-flop, so it dominates dynamic power.
• Clock quality (skew, jitter, transition time) directly determines the maximum operating frequency and timing margin of the design.

CTS Objectives

• Skew Minimization: All flip-flops should see the clock edge at approximately the same time. Target skew depends on the clock period — typically <5% of the period.
• Insertion Delay Control: Total delay from clock source to leaf flip-flops should be reasonable and consistent.
• Transition Time: Clock edges should be sharp (fast rise/fall) — slow edges increase short-circuit power and degrade timing margins.
• Power Optimization: Minimize the number and size of clock buffers — clock tree power can be 30–50% of total dynamic power.
• DRV Fixing: Ensure all clock nets meet design rule constraints (max capacitance, max transition, max fanout).

CTS Methodology

• Clustering: Group nearby flip-flops into clusters that share a common clock buffer.
• Buffer/Inverter Insertion: Insert a tree of buffers (or inverters for balanced rise/fall) to drive the clock from the source to all clusters.
• Balancing: Adjust buffer sizes, wire lengths, and topology to equalize delay to all sinks.
• NDR (Non-Default Rules): Route clock wires with wider width and spacing for better signal quality and reduced coupling.
• Shielding: Add grounded guard wires adjacent to clock routes for noise isolation.
• Multi-Source CTS: For large designs, use multiple clock roots (from a clock mesh or multiple PLLs) to reduce tree depth.

Clock Tree Topologies

• Balanced Tree (H-Tree): Symmetric branching where each branch has equal length — inherently low skew.
• Mesh: A grid of interconnected clock wires — low skew through averaging, but higher power.
• Spine: A central spine with branches — used for structured layouts.
• Hybrid: Combination of tree and mesh — mesh at the top level for global balance, trees at the local level for efficiency.

CTS in the Design Flow

• CTS runs after placement and before or during routing — flip-flop locations must be known.
• Pre-CTS Timing: Timing is estimated with ideal (zero-skew) clocks.
• Post-CTS Timing: Real clock tree delays and skew are included — timing may change significantly.
• Post-CTS Optimization: Additional optimization (gate sizing, buffer insertion, useful skew) to fix timing violations introduced by real clock delays.

Clock tree synthesis is arguably the most impactful single step in physical design — the quality of the clock tree directly determines chip frequency, power, and timing closure difficulty.