CMOS Process — the step-by-step fabrication methodology for building Complementary Metal-Oxide-Semiconductor integrated circuits, the dominant technology for modern digital and analog chips.

What Is CMOS?

CMOS (Complementary MOS) pairs NMOS and PMOS transistors together so that in any logic state, one transistor type is OFF — meaning static power consumption is near zero. This complementary design is why CMOS dominates: billions of transistors can operate without melting the chip. Every modern processor, memory chip, and SoC uses CMOS technology.

CMOS Process Flow

1. Substrate Preparation

• Start with a p-type silicon wafer (300mm diameter for advanced nodes).
• Grow a thin epitaxial silicon layer for uniform crystal quality.
• Create isolation structures (STI — Shallow Trench Isolation) by etching trenches and filling with oxide to electrically separate individual transistors.

2. Well Formation

• N-well: Implant phosphorus ions into regions where PMOS transistors will be built. The n-well provides the correct substrate polarity for PMOS operation.
• P-well: Implant boron ions for NMOS regions (in twin-well processes).
• Drive-in Anneal: High-temperature step (~1000C) to diffuse dopants to the desired depth and activate them.

3. Gate Stack Formation

• Gate Oxide: Grow ultra-thin oxide layer (historically SiO2, now high-k dielectrics like HfO2 at ~1-2nm equivalent oxide thickness).
• Gate Electrode: Deposit polysilicon (legacy) or metal gate (modern HKMG — High-K Metal Gate process). Metal gates eliminate poly depletion and improve performance.
• Gate Patterning: Lithography and etch define the gate length — the critical dimension that determines the technology node. At 7nm and below, EUV lithography and multi-patterning are required.

4. Source/Drain Formation

• LDD (Lightly Doped Drain): Low-dose implant to reduce hot-carrier effects at the drain edge.
• Spacer Formation: Deposit and etch silicon nitride spacers on gate sidewalls to offset the heavy source/drain implant from the channel.
• Heavy Implant: High-dose arsenic (NMOS) or boron (PMOS) implant to form low-resistance source/drain regions.
• Activation Anneal: Rapid thermal anneal (RTA) or laser spike anneal to activate dopants while minimizing diffusion.

5. Silicidation (Salicide)

• Deposit a metal (cobalt, nickel, or titanium) and react it with exposed silicon to form low-resistance silicide contacts on gate, source, and drain. This reduces parasitic resistance that limits switching speed.

6. Contact and Local Interconnect

• Deposit interlayer dielectric (ILD).
• Etch contact holes down to silicided source/drain/gate.
• Fill with tungsten (W) plugs using CVD.
• This creates the vertical connections from transistors to the first metal layer.

7. Back-End-of-Line (BEOL) Metallization

• Build multiple metal layers (10-15+ layers at advanced nodes) using the dual-damascene process:
• Etch trenches and vias in low-k dielectric.
• Deposit barrier (TaN/Ta) and seed layers.
• Electroplate copper to fill trenches.
• CMP (Chemical Mechanical Polishing) to planarize.
• Lower metal layers (M1-M3): Fine pitch for local routing.
• Upper metal layers: Wider pitch for power distribution and global signals.

8. Passivation and Pad Formation

• Deposit final passivation layers (silicon nitride, polyimide) to protect the chip.
• Open bond pad windows for external connections (wire bonding or flip-chip bumps).

Advanced CMOS Variations

• FinFET (3D Transistor): The channel wraps around a vertical fin, providing better gate control. Standard from 22nm through 5nm nodes.
• Gate-All-Around (GAA/Nanosheet): Gate surrounds the channel on all four sides — better electrostatics than FinFET. Samsung 3nm GAA and Intel 20A RibbonFET.
• CFET (Complementary FET): Stack NMOS on top of PMOS vertically to reduce area by ~50%. Research stage for 1nm and beyond.
• Backside Power Delivery (BSPDN): Route power through the wafer backside, freeing front-side metal layers for signals. Intel PowerVia at Intel 20A.

The CMOS process is the manufacturing backbone of the semiconductor industry — a precisely choreographed sequence of deposition, patterning, etching, and implantation steps that transforms a bare silicon wafer into a chip containing billions of transistors.