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CMOS process (complementary metal-oxide-semiconductor process) is the manufacturing technology that builds both NMOS and PMOS transistors on the same silicon substrate to create logic gates that dissipate power only when switching — the foundation of every digital chip from microcontrollers to AI accelerators. The word "complementary" is the key: by pairing an NMOS pull-down network with a PMOS pull-up network, a CMOS gate draws near-zero static current because one network is always off. This property enabled the scaling from room-sized computers to billions of transistors in a pocket-sized phone.

Why CMOS dominates. Before CMOS, NMOS-only logic (1970s) drew static current through pull-up resistors in every gate — power scaled linearly with transistor count, making large chips impractical. CMOS eliminated this by using PMOS transistors as active pull-ups that turn off when the output is low. The only current flows during switching transitions (charging/discharging load capacitance), giving the power equation:

$$P_{\text{CMOS}} = \alpha \cdot C_L \cdot V_{DD}^2 \cdot f + V_{DD} \cdot I_{\text{leak}}$$

The first term (dynamic) is zero when the circuit is idle; the second (leakage) was negligible until ~90 nm, when thin gate oxides made tunneling current significant. Modern CMOS at 3–5 nm has leakage that can equal 20–40% of total power.

The CMOS process flow — major modules in sequence:

Module	What happens	Key steps	CFS simulator
Wafer prep	CZ-grown 300mm Si(100) ingot, sliced, polished	Crystal growth, CMP	—
STI isolation	Trench isolates adjacent transistors	Litho, etch, oxide fill, CMP	/simulate, /cmp
Well formation	Create N-well (for PMOS) and P-well (for NMOS)	Ion implant, drive-in anneal	(ion implantation keyword)
Gate stack	High-k dielectric + metal gate (HKMG)	ALD HfO₂, metal dep, litho, etch	/deposition, /lithography
Source/drain	Form S/D junctions + epitaxial SiGe (PMOS) or Si:P (NMOS)	Implant, anneal, selective epi	(ion implantation keyword)
Contact	Connect transistors to first metal	Contact etch, W or Co fill, CMP	/simulate, /cmp
BEOL (M1–M15)	Build copper interconnect stack (lines + vias)	Dual-damascene litho/etch, Cu ECD, CMP × 10–15 layers	/interconnect, /cmp, /lithography
Passivation + bumps	Protect die, form solder bumps for packaging	Nitride dep, bump plating	—
Test + package	Wafer probe, dice, package, final test	ATE, assembly	—

Gate-first vs gate-last (replacement metal gate). At 45 nm and below, the industry moved to high-k metal gate (HKMG) to replace the polysilicon/SiO₂ gate stack. Two approaches:

Gate-first: deposit HKMG before S/D formation. Simpler flow, but the metal gate must survive the high-temperature S/D anneal (~1000°C), limiting material choices.
Gate-last (RMG): form a dummy polysilicon gate, complete S/D processing, then remove the dummy and replace it with HKMG at low temperature. More complex (extra CMP steps), but allows optimal metal work-function tuning for both NMOS and PMOS. All leading-edge fabs (TSMC, Intel, Samsung) use gate-last at 14 nm and below.

FinFET CMOS (14–5 nm). At 22 nm (Intel) and 16 nm (TSMC), planar MOSFETs were replaced by FinFETs — a 3D transistor where the channel is a tall, narrow silicon fin gated on three sides. The CMOS process added:

Fin patterning (self-aligned multi-patterning for fin pitch < 30 nm)
Fin recess and STI reflow
Epitaxial raised S/D (SiGe for PMOS strain, Si:P for NMOS)
Multiple work-function metals (different for NMOS vs PMOS Vt flavors)

GAA nanosheet CMOS (3 nm and below). The latest evolution replaces fins with stacked horizontal nanosheets (see CFS gate-all-around keyword). The process adds:

Si/SiGe superlattice epitaxy
Inner-spacer formation (unique to GAA)
Selective SiGe channel release etch
Conformal HKMG deposition wrapping all 4 sides of each sheet

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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">CMOS Fabrication — Building Complementary Transistors</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">NMOS + PMOS paired in every gate — near-zero static power, the foundation of all digital logic</text>

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  <text x="450" y="244" fill="#f87171" font-size="8.5" font-weight="600">5. BEOL metallization</text>
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  <text x="580" y="318" fill="#8b98a5" font-size="8" text-anchor="middle">total: 80–100 litho layers, 3–4 months</text>
  <text x="580" y="332" fill="#6b7684" font-size="7.5" text-anchor="middle">any single defect across all steps = dead die</text>

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  <text x="380" y="368" fill="#e6edf3" font-size="10" font-weight="600" text-anchor="middle">Why CMOS Dominates</text>
  <text x="50" y="390" fill="#34d399" font-size="8.5">• Zero static power: one transistor always off → no current path from VDD to GND</text>
  <text x="50" y="406" fill="#60a5fa" font-size="8.5">• Rail-to-rail output: pulls fully to VDD or GND (full logic swing)</text>
  <text x="50" y="422" fill="#a78bfa" font-size="8.5">• Scalable: same structure from 10µm (1971) to 2nm (2025) — just smaller</text>

  <text x="380" y="452" fill="#6b7684" font-size="11" text-anchor="middle">CMOS is the only transistor technology that scaled for 50 years — every chip in existence uses it.</text>
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Process complexity and cost by node. A leading-edge CMOS process at 3 nm requires 80–100 mask layers, 500–1000 individual process steps, 2–3 months of cycle time per wafer lot, and costs 25,000–35,000 USD per 300 mm wafer. The fab itself costs 20–30 billion USD to build and equip. This extreme cost drives the foundry model: only TSMC, Samsung, and Intel can afford to develop and maintain leading-edge CMOS processes, and chip companies (NVIDIA, Apple, AMD, Qualcomm) design on those processes without owning fabs.

CMOS and the CFS platform. Every CFS simulator models a step in the CMOS process flow: the Etch Simulator (/simulate) models STI/gate/contact etch profiles, the Deposition Simulator (/deposition) models CVD/ALD film conformality, the Lithography Simulator (/lithography) models aerial-image resolution, the CMP Simulator (/cmp) models planarization after each fill step, and the Transistor Simulator (/transistor) models the electrical behavior of the finished CMOS device.

cmos processcmos fabricationcmos manufacturingcmos technologycmos basicscmos flow

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