Chemical Mechanical Planarization (CMP) is the semiconductor process that creates globally flat wafer surfaces by combining chemical etching (slurry chemistry) with mechanical abrasion (polishing pad) — essential for multi-layer lithography where each layer requires <5 nm surface topography across the 300 mm wafer, used repeatedly throughout the CMOS process flow for STI, ILD, tungsten, copper, and gate metal planarization, making CMP the most frequently used planarization technique with 15-30 CMP steps per chip at advanced nodes.

CMP Mechanism

The wafer (face down) is pressed against a rotating polyurethane pad while slurry (abrasive particles + chemicals) flows between them:

• Chemical Component: Oxidizers (H₂O₂), pH adjusters, complexing agents, corrosion inhibitors chemically modify the wafer surface. For Cu CMP: H₂O₂ oxidizes Cu to CuO, which is softer and more easily removed.
• Mechanical Component: Abrasive nanoparticles (colloidal silica 30-100 nm, or ceria/alumina) in the slurry physically remove the chemically weakened surface material. Pad asperities also contribute to material removal.
• Preston's Equation: Removal rate = Kp × P × V, where P = pressure, V = relative velocity, Kp = Preston coefficient (material and slurry dependent). Typical removal rates: 100-500 nm/min for oxide, 300-800 nm/min for Cu.

CMP Applications in CMOS Flow

• STI CMP: Planarize SiO₂ fill, stop on SiN hardmask. Slurry: high oxide-to-nitride selectivity (ceria slurry, 30:1+).
• ILD CMP: Planarize interlayer dielectric (oxide) before via lithography. Within-die planarity <10 nm.
• Tungsten CMP: Remove W overburden from contact/via fill. Stop on oxide. Slurry: acidic with Fe³⁺ or H₂O₂ oxidizer.
• Copper CMP: Multi-step process — (1) Bulk Cu removal (high rate), (2) Barrier removal (Ta/TaN selective), (3) Buff/clean (residual removal + surface finish). Cu CMP enables the damascene interconnect process that replaced subtractive aluminum etching at the 130 nm node.
• Gate Metal CMP: Remove excess metal gate after replacement metal gate fill. Stop on ILD.
• Poly CMP: Planarize polysilicon for gate patterning.

Key Challenges

• Dishing: Over-polishing causes the center of wide metal features (Cu pads) to be recessed below the surrounding dielectric. Magnitude: 10-50 nm depending on feature width. Mitigation: dummy fill patterns in design to reduce pattern density variation.
• Erosion: Dense arrays of narrow metal lines see higher local removal rate, thinning the dielectric between lines. Creates thickness variation across the die.
• Defects: Slurry particles can scratch the surface (micro-scratches reduce device yield). Pad debris and agglomerates cause deeper scratches. Post-CMP clean (megasonic + brush scrub + dilute HF + DI water) is critical.
• Endpoint Detection: Knowing precisely when to stop polishing. Methods: motor current monitoring (friction change when top layer clears), optical endpoint (reflectance change), eddy current (metal thickness measurement in real time).

Advanced CMP Innovations

• Multi-Zone Pressure: The CMP head applies different pressures across concentric zones of the wafer to compensate for incoming film thickness non-uniformity (thicker edge → more pressure at edge).
• In-Situ Metrology: Integrated thickness measurement during polishing enables real-time feedback control.
• Ceria Slurry: Cerium oxide particles for STI CMP provide chemical-mechanical synergy with exceptional oxide-to-nitride selectivity.

CMP is the universal planarization tool that makes multi-layer chip fabrication possible — without globally flat surfaces, advanced lithography (DOF <50 nm at EUV) and precise patterning of 10+ metal layers would be impossible, making CMP the process that literally smooths the way for everything built on top of it.