Cobalt Interconnect Overview

Cobalt (Co) is used as an alternative metal for the smallest vias and local interconnect levels at advanced nodes (7nm and below) where copper's resistivity advantage disappears due to grain boundary and surface scattering effects.

Why Cobalt?

• Via Resistance: Cu vias at < 20nm diameter have very high resistance due to the thick TaN/Ta barrier consuming most of the via volume. Co can be deposited barrierless or with ultra-thin barriers.
• No Barrier Needed: Co does not diffuse into SiO₂/low-k dielectrics as readily as Cu, enabling thinner or no barrier layers.
• Better Fill: CVD cobalt fills small vias void-free (bottom-up growth), while Cu electroplating struggles with small, high-aspect-ratio features.
• Electromigration: Co has excellent EM resistance at the via level.

Where Cobalt Is Used

• Contact level (M0): Direct metal contact to transistor source/drain and gate. Intel introduced Co contacts at 10nm.
• Via0: Connecting M0 to M1. Co provides lower via resistance than Cu at this scale.
• Local interconnect: M1 and potentially M2 at the most advanced nodes.
• Upper metals: Still Cu (wider wires where Cu resistivity advantage remains).

Cobalt Process

1. CVD Cobalt: Deposit Co by chemical vapor deposition (dicobalt hexacarbonyl tert-butylacetylene or similar precursor). 2. Anneal: Reflow/grain growth at 300-400°C to reduce resistivity. 3. CMP: Polish overburden. Co CMP uses different slurry chemistry than Cu CMP.

Limitations

• Bulk resistivity: Co (6.2 μΩ·cm) is higher than Cu (1.7 μΩ·cm). Only advantageous at the smallest dimensions where barrier volume dominates.
• Cost: CVD Co is more expensive than Cu electroplating.