Contact Silicide Technology encompasses the formation of low-resistivity metal-silicon compounds (NiSi, NiPtSi, TiSi2, CoSi2) at the source/drain and gate contact interfaces to reduce parasitic contact resistance — a critical performance parameter that becomes increasingly dominant as transistor dimensions shrink and contact areas decrease proportionally.

The silicidation process involves depositing a thin metal film (Ni, NiPt, Ti, or Co) on exposed silicon surfaces, followed by thermal annealing to drive a solid-state reaction between the metal and silicon, forming a silicide compound. Unreacted metal on dielectric surfaces is selectively removed by wet etch (typically H2SO4/H2O2 or HNO3-based), leaving silicide only where metal contacted silicon — this self-aligned silicide (salicide) process automatically forms contacts without additional lithography.

Nickel silicide (NiSi) and its platinum-alloyed variant NiPtSi are the dominant silicide technologies at nodes from 65nm through current FinFET generations. NiSi forms in a two-step anneal: first anneal at 250-350°C forms Ni₂Si (metal-rich, high-resistivity phase); selective wet etch removes unreacted Ni; second anneal at 400-500°C converts Ni₂Si to the desired low-resistivity NiSi phase (~14 μΩ·cm). The Pt addition (5-10% Pt in the Ni film) stabilizes NiSi against transformation to the high-resistivity NiSi₂ phase during subsequent thermal processing and improves morphological stability.

For FinFET and GAA architectures, silicidation faces unique challenges: the S/D epitaxial surfaces have complex 3D geometry (diamond- or sigma-shaped epi facets for FinFETs, merged or unmerged fins), and silicide must form uniformly on these non-planar surfaces. The thin nanosheet dimensions (~5-7nm) limit how much silicon can be consumed by silicidation without completely converting the channel. Contact resistance reduction strategies include: Ti silicide (TiSi) revisited at sub-5nm nodes due to lower Schottky barrier height to n-Si; wrap-around contacts that maximize the contact area to the 3D S/D surface; and interface engineering using heavy doping and dopant segregation at the silicide/Si interface to reduce the Schottky barrier.

Contact resistivity (ρc) scaling is the fundamental challenge: as contact area shrinks (from ~1000nm² at 7nm node to ~200nm² at 2nm), the contact resistance Rc = ρc/Ac increases proportionally. Achieving ρc below 1×10⁻⁹ Ω·cm² requires: active dopant concentration >5×10²⁰ cm⁻³ at the silicide interface, optimized silicide phase and grain structure, and minimal interfacial oxide. Research approaches include metallic S/D contacts (no silicide — direct metal to heavily doped semiconductor) and 2D material contacts using semimetals (Bi, Sb) for de-pinned Schottky barrier reduction.

Contact silicide technology continues to evolve as the critical resistance bottleneck in advanced transistors — the silicide interface is where electrons transition from metal to semiconductor, and its quality determines how efficiently each transistor can drive current to the interconnect network above.