CFET — the complementary FET — is the transistor architecture the industry expects to follow the nanosheet gate-all-around device, the next rung on a scaling ladder that already climbed from planar to FinFET to GAA. Its defining idea is vertical. Instead of placing the n-type and p-type transistors of a CMOS pair side by side on the wafer the way every generation before it did, a CFET stacks one directly on top of the other, folding the pair into a single footprint and roughly halving the area a standard logic cell needs. It is less a new way to build one transistor than a new way to pack the complementary pair that all CMOS logic is made of — the moment when transistor scaling stops being about shrinking a feature and turns explicitly three-dimensional.\n\nTransistor scaling has advanced mainly by improving gate control, and GAA nanosheet is the current best. The ladder is a story of wrapping the gate ever more tightly around the channel so it can shut off leakage at ever-shorter lengths: planar gates touched the channel on one side, FinFET on three sides of a vertical fin, and gate-all-around nanosheet (also called GAAFET or RibbonFET) wraps all four sides of a stack of horizontal sheets. Nanosheet is the leading-edge device at the 2 nm-class node, and its drive strength is tunable simply by making the sheets wider. But fully wrapping the gate is close to the limit of what can be done to a single channel — further density has to come from somewhere else.\n\nForksheet is an incremental step: pack the nFET and pFET closer by putting a dielectric wall between them. Before committing to vertical stacking, the forksheet keeps the two device types side by side but separates them with a dielectric wall, which lets the n-to-p spacing shrink below what a standard GAA layout allows. It is a density bridge between nanosheet and CFET that reuses most of the nanosheet process flow — a modest, lower-risk gain that buys area while the harder CFET integration matures.\n\nCFET is the leap: stack the nFET directly on top of the pFET so the CMOS pair occupies one footprint. In a complementary FET the two transistors of an inverter or CMOS pair are built vertically, one above the other, sharing the same silicon area — which roughly halves the standard-cell height (fewer routing tracks) and shortens the wiring between the pair. Two integration flavors compete: monolithic CFET grows both devices in one continuous sequence, while sequential (stacked) CFET builds the bottom device, bonds or transfers a layer, and builds the top device on top. Most roadmaps place CFET at the 1 nm-class (A-series) nodes.\n\nCFET's promise is area, but its price is process complexity and thermal and parasitic challenges. Stacking two devices doubles many vertical process steps, demands extreme aspect-ratio etches, and requires buried or backside contacts to reach the bottom transistor. The thermal budget becomes delicate — building the top device must not damage the one beneath it — and self-heating rises when devices sit on top of each other with less path to the substrate. Routing signals to a buried transistor is genuinely hard. These are precisely the reasons CFET is described as "next" rather than "now."\n\nCFET, GAA, and backside power are complementary moves in the same 3D turn of scaling. The through-line ties them together: once you can no longer make a single transistor meaningfully better, you stack and rearrange in the third dimension. Gate-all-around wrapped the gate; forksheet squeezed the pair; CFET stacks the pair outright; backside power delivery moves the power network behind the wafer; and hybrid bonding stacks whole dies. Together they mark scaling shifting from shrinking features to folding the device and its wiring into the vertical axis — and that density feeds AI silicon directly, packing more logic and SRAM into every square millimeter.\n\n| Device | Gate control | n / p arrangement | Relative cell area | Status |\n|---|---|---|---|---|\n| Planar | 1 side | Side by side | Baseline (large) | Legacy |\n| FinFET | 3 sides (fin) | Side by side | Smaller | ~2011–2022 nodes |\n| GAA nanosheet | 4 sides (full wrap) | Side by side | Smaller still | 2 nm-class (now) |\n| Forksheet | 4 sides + dielectric wall | Side by side, closer | ~10–20% denser | Bridge step |\n| CFET | 4 sides (wrap) | n stacked on p (3D) | ~½ (stacked pair) | 1 nm-class (next) |\n\n``svg\n\n``\n\nThe unhelpful way to read CFET is as merely the next node's transistor, one more shrink in a long line of shrinks. The useful way is to see the point where the shrink changes direction: for decades scaling wrapped the gate more tightly around a single channel — one side, three sides, then all four with GAA nanosheet — but once the gate fully surrounds the channel there is little left to wrap, so the industry turns the CMOS pair on its side and stacks the nFET on top of the pFET, halving the footprint in the one dimension still free. Forksheet is the cautious half-step; CFET is the commitment; and it rhymes with backside power and die stacking, all of which move structure into the vertical axis. Read CFET through a scaling-just-turned-3D lens rather than a yet-another-node lens, and GAA, forksheet, the stacked pair, and their thermal and contact headaches stop looking like disconnected roadmap items and resolve into one: when you run out of room sideways, you build up.