CXL (Compute Express Link) is an open interconnect standard that lets CPUs, accelerators, and memory devices share a coherent view of memory over the physical PCIe wire. Ordinary PCIe moves data between a host and a device as explicit, non-coherent transfers; CXL adds cache coherence and native load/store access, so a GPU can coherently cache host memory and a CPU can read and write memory that physically lives on an attached device as if it were local DRAM. It is the interconnect the industry is standardizing on to break memory out of the box, and a foundational technology for large AI and disaggregated data-center systems.\n\n``svg\n\n``\n\nCXL runs three sub-protocols over the same PCIe electricals. CXL.io handles discovery, configuration, and bulk DMA and is essentially PCIe — every CXL link needs it. CXL.cache lets a device coherently cache the host's memory, so an accelerator's local copies stay consistent with the CPU. CXL.mem lets the host issue direct load/store operations to memory attached to a device. Because it reuses the PCIe physical layer, CXL rides on the same connectors and lanes servers already have.\n\nDevices come in three types depending on which protocols they use. Type 1 devices (io + cache) are accelerators like smart NICs that need coherent access to host memory but bring no memory of their own. Type 2 devices (io + cache + mem) are accelerators such as GPUs that both cache host memory and expose their own memory to the host — the richest case. Type 3 devices (io + mem) are pure memory expanders that add capacity or bandwidth to a host without any compute.\n\nCoherence is the feature that makes it more than fast PCIe. Hardware keeps caches consistent across the CPU and attached devices automatically, so software can use a single shared address space instead of manually copying buffers back and forth and worrying about stale data. This dramatically simplifies programming heterogeneous systems and removes a major source of overhead in accelerator pipelines.\n\nMemory expansion and pooling are the headline data-center use cases. A Type 3 expander can add terabytes of DRAM (or cheaper/denser media) to a server that has run out of DIMM slots. With a CXL switch, a pool of memory can be shared across many hosts and allocated to whichever one needs it right now — turning "stranded" memory that sits idle on one server into a fungible, disaggregated resource. For memory-hungry AI training and inference and for in-memory databases, this directly attacks cost and capacity limits.\n\nThe trade-off is latency, and the standard is still maturing. Reaching memory across a CXL link is slower than a local DIMM — comparable to a distant NUMA node — so CXL memory is best used as a tier below main memory rather than a drop-in replacement. Successive generations (CXL 2.0 added switching and pooling; CXL 3.x added fabrics, multi-level switching, and peer-to-peer) are steadily expanding what the fabric can do as hardware support broadens across CPUs and devices.\n\n| Sub-protocol | Who accesses whom | Coherent? | Purpose |\n|---|---|---|---|\n| CXL.io | host ↔ device | no | discovery, config, DMA (PCIe) |\n| CXL.cache | device caches host memory | yes | accelerator coherence |\n| CXL.mem | host load/store on device memory | yes | memory expansion / pooling |\n\nRead CXL through a shared-coherent-memory lens rather than a faster-bus lens: the point is not raw bandwidth over PCIe but that memory stops being trapped behind a device boundary. Once a CPU and an accelerator agree on one coherent address space, and once capacity can be pooled and reassigned across servers, memory becomes a disaggregated resource you provision independently of compute — which is exactly what large, memory-bound AI systems need.\n