Compute in memory. moves selected computation into or immediately beside memory arrays so that operands do not repeatedly traverse the conventional processor–memory boundary. The term covers analog matrix operations inside nonvolatile crossbars, mixed-signal or digital arithmetic inside SRAM macros, logic placed near DRAM banks, and processing units integrated with stacked high-bandwidth memory. The benefit is workload-dependent: reducing bytes moved can cut latency and energy for data-intensive kernels, but host orchestration, activation movement, conversion, control, synchronization, and unsupported operations remain. A useful engineering specification separates intrinsic material behavior from device geometry, contacts, interfaces, interconnect, packaging, and workload. Headline mobility, bandgap, critical temperature, optical yield, or switching energy measured on a research structure does not directly predict a manufactured product. Designers need distributions across wafers and lots, temperature and bias dependence, parasitic resistance and capacitance, hysteresis, aging, variability, defect sensitivity, and the energy and latency of every driver, converter, controller, and data transfer. Compact models must be calibrated inside the operating region and must expose uncertainty instead of turning one favorable demonstration into a universal constant.

Physical mechanism. In an analog resistive crossbar, each cell conductance represents a weight. Input values become row voltages; cell current follows Ohm law; currents sum on each column by Kirchhoff current law, producing dot products in parallel. Signed weights need differential cells or offset coding, and multibit values need multiple levels, bit slicing, time encoding, or repeated cycles. ReRAM, phase-change memory, floating-gate devices, and other elements offer different programming, retention, endurance, drift, and variability. DACs, transimpedance amplifiers, ADCs, accumulators, activation units, and calibration can dominate area and energy. Integration is usually the decisive constraint. Thermal budget, ambient chemistry, surface preparation, film stress, coefficient-of-expansion mismatch, contamination rules, lithographic alignment, etch selectivity, contact formation, encapsulation, planarization, and backend compatibility determine whether a promising layer can join a CMOS or display process. Architecture then determines whether its advantage survives peripheral circuits and packaging. A complete path includes materials sourcing, deposition or growth, patterning, metrology, electrical test, assembly, calibration, firmware or compiler support, repair and redundancy, and end-of-life handling. Pilot-line learning matters because yield loss can scale faster than active area.

Device and process implementation. Digital SRAM compute modifies bitcells or periphery to perform Boolean operations, bit-serial multiplication, popcount, or partial accumulation while retaining more deterministic behavior. Near-memory engines beside SRAM, DRAM, or HBM preserve standard arrays and add programmable logic with high local bandwidth. Mapping software tiles tensors across finite arrays, handles positive and negative values, precision, sparsity, faults, activation functions, normalization, communication, and accumulation. Compiler cost models must know array dimensions, converter precision, bank conflicts, data layout, endurance, calibration state, and fallback costs rather than treating the accelerator as an ideal matrix instruction. Verification spans atom to system. Structural and chemical evidence can include diffraction, spectroscopy, microscopy, thickness mapping, composition, surface roughness, grain statistics, and contamination analysis. Electrical and optical characterization sweeps voltage, current, frequency, temperature, field, wavelength, time, and geometry; pulsed tests separate trapping and self-heating from steady-state behavior. Reliability plans use accelerated stress with a justified physical model, large enough populations, controls, censored-data handling, and failure analysis. Circuit tests include corners and Monte Carlo variation, while system tests measure useful work, latency, energy, quality, thermal throttling, recovery, and degradation under representative workloads.

Applications and architectural trade-offs. Neural inference is a prominent target because convolution, linear layers, and attention projections reuse weights in matrix–vector products. Database filters, graph traversal, recommendation embeddings, signal processing, search, and scientific stencils may benefit from other PIM forms. Analog arrays can deliver high local operation density at modest precision; digital SRAM offers control and integration but lower density; HBM-PIM provides capacity and bandwidth near mature memory; near-memory accelerators support broader operations while moving data farther. Training adds stricter precision, update endurance, optimizer state, and collective communication. Technology selection should use a declared baseline and boundary. The comparison records feature size, substrate, area, operating point, cooling, precision, lifetime criterion, duty cycle, peripherals, package, manufacturing maturity, and whether reported values are measured, simulated, or projected. Teams should ask which bottleneck is removed, which new bottleneck appears, how failures are detected and contained, whether calibration is stable, and what fallback exists. Reproducible artifacts include process splits, masks, recipes, material lots, model versions, test code, raw traces, analysis notebooks, and traceability from sample to plotted result.

<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,BlinkMacSystemFont,Segoe UI,Roboto,sans-serif">
  <rect width="760" height="470" fill="#0d1117" rx="8"/>
  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Processing-In-Memory (PIM) Memory-Side Accelerator</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">Integrating SIMD Compute Units Directly Inside DRAM Banks / HBM Base Logic Dies</text>

  <g transform="translate(30, 70)">
    <rect width="330" height="350" fill="#161b22" stroke="#30363d" stroke-width="1.5" rx="6"/>
    <text x="165" y="25" fill="#79c0ff" font-size="14" font-weight="600" text-anchor="middle">1. Bank-Level PIM Architecture</text>

    <g transform="translate(20, 45)">
      <rect width="290" height="180" fill="#0d1117" stroke="#30363d" rx="4"/>

      <!-- DRAM Bank -->
      <rect x="30" y="30" width="100" height="120" fill="#1f6feb" opacity="0.6" rx="3"/>
      <text x="80" y="95" fill="#fff" font-size="11" font-weight="700" text-anchor="middle">DRAM Bank</text>

      <line x1="130" y1="90" x2="160" y2="90" stroke="#79c0ff" stroke-width="2"/>

      <!-- PIM Engine -->
      <rect x="160" y="30" width="100" height="120" fill="#238636" opacity="0.8" rx="3"/>
      <text x="210" y="75" fill="#fff" font-size="10" font-weight="700" text-anchor="middle">PIM SIMD</text>
      <text x="210" y="95" fill="#fff" font-size="9" text-anchor="middle">FP16 ALU</text>
      <text x="210" y="115" fill="#fff" font-size="8" text-anchor="middle">MAC / Adders</text>
    </g>

    <rect x="20" y="245" width="290" height="90" fill="#0d1117" stroke="#30363d" rx="4"/>
    <text x="165" y="265" fill="#3fb950" font-size="12" font-weight="600" text-anchor="middle">Internal Bank Bandwidth (TB/s)</text>
    <text x="165" y="285" fill="#8b98a5" font-size="10" text-anchor="middle">Processes Data directly inside NVM / DRAM Bank</text>
    <text x="165" y="305" fill="#e6edf3" font-size="11" text-anchor="middle">Bypasses Off-Chip Bus Bottlenecks</text>
  </g>

  <g transform="translate(380, 70)">
    <rect width="350" height="350" fill="#161b22" stroke="#30363d" stroke-width="1.5" rx="6"/>
    <text x="175" y="25" fill="#79c0ff" font-size="14" font-weight="600" text-anchor="middle">2. Target Workloads &amp; Speedup</text>

    <rect x="20" y="45" width="310" height="120" fill="#0d1117" stroke="#30363d" rx="4"/>
    <text x="175" y="68" fill="#58a6ff" font-size="11" font-weight="600" text-anchor="middle">Memory-Bound Operator Offload</text>
    <text x="175" y="90" fill="#8b98a5" font-size="10" text-anchor="middle">Vector Addition, Element-wise Multiplication</text>
    <text x="175" y="110" fill="#8b98a5" font-size="10" text-anchor="middle">LLM KV Cache Generation Phase</text>
    <text x="175" y="130" fill="#3fb950" font-size="10" font-weight="600" text-anchor="middle">Recommender System Embedding Lookups</text>

    <rect x="20" y="180" width="310" height="155" fill="#0d1117" stroke="#30363d" rx="4"/>
    <text x="175" y="200" fill="#d2a8ff" font-size="11" font-weight="600" text-anchor="middle">System-Level Benefits</text>
    <text x="175" y="225" fill="#8b98a5" font-size="10" text-anchor="middle">1. 80%+ Reduction in Host Memory Channel Traffic</text>
    <text x="175" y="245" fill="#8b98a5" font-size="10" text-anchor="middle">2. 4x Reduction in Energy per Compute Task</text>
    <text x="175" y="265" fill="#8b98a5" font-size="10" text-anchor="middle">3. HBM-PIM / Aquabolt-XL Standard Commercialization</text>
    <text x="175" y="295" fill="#3fb950" font-size="10" font-weight="600" text-anchor="middle">Exascale AI Acceleration</text>
  </g>

  <text x="380" y="452" fill="#6b7684" font-size="11" text-anchor="middle">Processing-In-Memory Architecture Overcoming Memory Wall Latency in Data-Intensive AI Applications</text>
</svg>

Measurement, reliability, and deployment. Validation begins with a bit-accurate or device-aware reference model and covers quantization, clipping, saturation, signed encoding, accumulation order, ADC transfer, noise, conductance error, drift, nonlinear writes, stuck cells, temperature, IR drop, sneak paths, and endurance. Calibration data must not leak test inputs or hide aging. Silicon tests separate array core, converters, interconnect, digital support, and host overhead; report application accuracy, tail latency, throughput, energy, area, utilization, reprogramming, and cooling at the same quality target as the baseline. Recovery includes remapping, spare rows, retraining, recalibration, or digital fallback. Integration is usually the decisive constraint. Thermal budget, ambient chemistry, surface preparation, film stress, coefficient-of-expansion mismatch, contamination rules, lithographic alignment, etch selectivity, contact formation, encapsulation, planarization, and backend compatibility determine whether a promising layer can join a CMOS or display process. Architecture then determines whether its advantage survives peripheral circuits and packaging. A complete path includes materials sourcing, deposition or growth, patterning, metrology, electrical test, assembly, calibration, firmware or compiler support, repair and redundancy, and end-of-life handling. Pilot-line learning matters because yield loss can scale faster than active area. Verification spans atom to system. Structural and chemical evidence can include diffraction, spectroscopy, microscopy, thickness mapping, composition, surface roughness, grain statistics, and contamination analysis. Electrical and optical characterization sweeps voltage, current, frequency, temperature, field, wavelength, time, and geometry; pulsed tests separate trapping and self-heating from steady-state behavior. Reliability plans use accelerated stress with a justified physical model, large enough populations, controls, censored-data handling, and failure analysis. Circuit tests include corners and Monte Carlo variation, while system tests measure useful work, latency, energy, quality, thermal throttling, recovery, and degradation under representative workloads. Technology selection should use a declared baseline and boundary. The comparison records feature size, substrate, area, operating point, cooling, precision, lifetime criterion, duty cycle, peripherals, package, manufacturing maturity, and whether reported values are measured, simulated, or projected. Teams should ask which bottleneck is removed, which new bottleneck appears, how failures are detected and contained, whether calibration is stable, and what fallback exists. Reproducible artifacts include process splits, masks, recipes, material lots, model versions, test code, raw traces, analysis notebooks, and traceability from sample to plotted result. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.