Computer architecture is the discipline of designing the structure, organization, and instruction-level behavior of a processor — defining how hardware executes software by specifying the instruction set (ISA), the datapath (ALU, registers, pipeline stages), the memory hierarchy (caches, DRAM, storage), and the control logic that orchestrates them. Every AI accelerator, CPU, GPU, and SoC is a product of computer architecture decisions that trade off performance, power, area, and programmability. The field spans from single-core pipeline design to thousand-chip datacenter-scale systems.
The three levels of computer architecture:
| Level | What is defined | Who decides | Example |
|---|---|---|---|
| ISA (instruction set architecture) | The programmer-visible contract: instructions, registers, addressing modes, data types | Architecture committee (ARM, RISC-V, x86) | ARMv9, RV64GCV, x86-64 |
| Microarchitecture | How the ISA is implemented: pipeline depth, execution units, caches, branch predictor, OoO engine | Chip design team | Apple M4, AMD Zen 5, Intel P-core |
| System architecture | Multi-core, interconnect, memory controllers, I/O, accelerators, coherence protocol | SoC/system architect | NVIDIA Grace-Hopper, Apple M4 Ultra |
The CPU pipeline — where instructions become results. A modern high-performance CPU core processes instructions through 15–25 pipeline stages:
Fetch → Decode → Rename → Dispatch → Issue → Execute → Memory → Writeback → Commit
Out-of-order execution allows the processor to look ahead (200+ instructions in the reorder buffer) and execute whichever instructions have their operands ready, regardless of program order — hiding memory latency and keeping functional units busy. This is what makes a CPU fast on irregular, branch-heavy code (unlike GPUs which rely on massive parallelism of regular threads).
Memory hierarchy — hiding the DRAM latency gap. DRAM takes ~60–100 ns to respond, but a CPU core at 5 GHz executes one instruction every 0.2 ns — a 300–500× mismatch. The cache hierarchy bridges this gap:
| Level | Size | Latency (cycles) | Bandwidth | Role |
|---|---|---|---|---|
| L1 (per core) | 32–64 KB I + D | 4–5 cycles | ~1 TB/s | Hot working set |
| L2 (per core) | 256 KB – 2 MB | 12–15 cycles | ~500 GB/s | Recent misses |
| L3 (shared) | 4–128 MB | 30–50 cycles | ~200 GB/s | Cross-core sharing |
| HBM/DRAM | 16–192 GB | 100–200 cycles | 50–8000 GB/s | Full dataset |
| Storage (SSD) | TB-scale | 10,000+ cycles | 10–50 GB/s | Persistent data |
GPU architecture — throughput over latency. While CPUs optimize for single-thread speed (deep pipeline, big caches, branch prediction), GPUs optimize for aggregate throughput: thousands of simple threads executing the same instruction on different data (SIMT). This makes GPUs ideal for deep learning (where the workload is millions of independent multiply-accumulate operations on matrix tiles). The trade-off: any single thread is slow (high latency to memory), but the GPU hides latency by switching between thousands of threads every cycle.
AI accelerator architecture — beyond GPU. Purpose-built AI chips (Google TPU, Tesla Dojo, Cerebras WSE) go further than GPUs by removing general-purpose features (branch prediction, scalar units, fine-grained threading) and dedicating all transistor area to matrix-multiply units + HBM bandwidth. The CFS Systolic-Array Simulator at /systolic models exactly this trade-off: how PE array size, memory bandwidth, and dataflow choice determine achieved TOPS and utilization.
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Computer architecture and the CFS platform. CFS models the hardware that computer architecture produces: the Transistor Simulator (/transistor) gives the device physics beneath the logic gates; the Systolic-Array Simulator (/systolic) models the AI accelerator's compute engine; the HBM Simulator (/hbm) models the memory subsystem; and the Inference Simulator (/infer) models the full-system serving throughput. Understanding architecture — the decisions about pipelines, caches, parallelism, and dataflow — is what separates an engineer who uses chips from one who designs them.
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