Contact Formation — creating vertical connections (plugs) from the first metal layer down to the transistor's source, drain, and gate, bridging the front-end (transistors) and back-end (wiring) of the chip.

Process

1. Deposit inter-layer dielectric (ILD) over completed transistors 2. Planarize with CMP to create flat surface 3. Pattern and etch contact holes (high aspect ratio: ~10:1 at advanced nodes) 4. Deposit barrier layer (TiN) to prevent metal diffusion 5. Fill with tungsten (W) using CVD 6. CMP to remove excess tungsten — contact plugs remain

Challenges

• Alignment: Contact must land accurately on tiny source/drain and gate areas
• Aspect ratio: Deep, narrow holes are difficult to fill without voids
• Contact resistance: Shrinking contact area → rising resistance at every node

Self-Aligned Contact (SAC)

• Uses etch selectivity between contact etch stop layer (SiN cap on gate) and ILD
• Contact can overlap the gate without shorting — the SiN cap protects it
• Essential at advanced nodes where overlay accuracy is insufficient for tight spacing

Scaling Trends

• Tungsten alternatives: Cobalt (Co), Ruthenium (Ru) for lower resistance at small dimensions
• MOL (Middle-of-Line): New naming for the contact/local interconnect layers between FEOL and BEOL

Contact formation is the critical handoff between the transistor world and the interconnect world — the interface must be low resistance and perfectly aligned.