Contact Formation is the multi-step process of creating low-resistance electrical connections between metal interconnect layers and the underlying source/drain/gate regions — involving high-aspect-ratio dielectric etching, barrier/liner deposition, tungsten fill, and chemical-mechanical polishing to achieve contact resistances below 100Ω per contact at sub-20nm contact dimensions.
Contact Etch Process:
- Dielectric Stack: pre-metal dielectric (PMD) typically consists of 50-150nm silicon nitride etch stop layer over source/drain, followed by 200-500nm of silicon oxide (TEOS, USG, or low-k material); total etch depth 250-650nm with contact diameter 30-80nm creates aspect ratios of 5:1 to 15:1
- Lithography: contact patterning uses 193nm immersion lithography with optical proximity correction (OPC) and sub-resolution assist features (SRAF); at advanced nodes (<28nm), contact holes are below lithographic resolution and require pitch-splitting or EUV lithography
- Etch Chemistry: fluorocarbon plasma (C₄F₈/CH₂F₂/Ar/O₂) for oxide etch with high selectivity to nitride etch stop (>20:1); etch stops on nitride over silicide; subsequent breakthrough etch removes nitride with CHF₃/O₂ chemistry selective to silicide
- Profile Control: tapered contact profile (80-85° sidewall angle) improves barrier/liner conformality and tungsten fill; pulsed plasma, controlled polymer deposition, and multi-step etch recipes manage profile while maintaining critical dimension (CD) control
Barrier and Liner Deposition:
- Barrier Requirements: prevents tungsten diffusion into silicon (forms high-resistivity WSi₂), provides adhesion for tungsten, and maintains low contact resistance; must be conformal in high-aspect-ratio contacts with step coverage >90%
- TiN/Ti Stack: traditional barrier consists of 5-10nm Ti (adhesion and silicide formation) followed by 5-15nm TiN (diffusion barrier); physical vapor deposition (PVD) at 200-400°C; Ti reacts with NiSi to form low-resistance TiSi₂ interface
- TaN/Ta Barrier: tantalum-based barriers provide better diffusion blocking than Ti/TiN; 3-5nm Ta adhesion layer followed by 5-10nm TaN; superior performance but higher resistivity (200 μΩ·cm for TaN vs 50 μΩ·cm for TiN)
- ALD Barriers: atomic layer deposition of TiN or TaN at 300-400°C provides superior conformality (>95% step coverage) in high-aspect-ratio contacts; critical for sub-40nm contacts where PVD conformality is insufficient
Tungsten Fill:
- Nucleation Layer: thin tungsten nucleation (5-20nm) by PVD or CVD ensures continuous coverage over the barrier; PVD provides better adhesion but poor step coverage; CVD nucleation using WF₆/SiH₄ or WF₆/B₂H₆ provides conformal coverage
- Bulk CVD Fill: WF₆ + H₂ → W + HF at 350-450°C fills the contact; hydrogen reduction provides void-free fill with low resistivity (8-12 μΩ·cm); process pressure (10-100 Torr) and temperature control fill profile and minimize voids
- Bottom-Up Fill: for high-aspect-ratio contacts (>8:1), bottom-up fill using selective CVD chemistry prevents void formation; additives (PH₃, B₂H₆) promote bottom nucleation and suppress sidewall deposition
- Seam and Void Control: improper fill conditions create centerline seams or voids that increase resistance and reduce reliability; optimized nucleation, temperature ramping, and multi-step fill recipes minimize defects
Chemical-Mechanical Polishing:
- Tungsten CMP: removes excess tungsten and planarizes the surface for subsequent metal layer deposition; slurry contains alumina or silica abrasives (50-200nm particles) with oxidizers (H₂O₂, Fe(NO₃)₃) and complexing agents
- Selectivity Requirements: W:oxide selectivity of 20:1 to 50:1 prevents oxide erosion; W:TiN selectivity of 10:1 to 20:1 provides endpoint detection when tungsten is cleared and TiN is exposed
- Dishing and Erosion: large contact arrays experience dishing (center removal faster than edges) and erosion (pattern-dependent removal rates); dummy fill patterns and CMP-aware design rules minimize topography
- Endpoint Detection: optical or eddy-current sensors detect when tungsten is cleared; overpolishing removes barrier layer and increases contact resistance; underpolishing leaves tungsten residues causing shorts
Contact Resistance Optimization:
- Specific Contact Resistivity: ρc = 1-5×10⁻⁸ Ω·cm² for NiSi contacts with proper barrier and high S/D doping (>10²⁰ cm⁻³); contact resistance Rc = ρc/Area + spreading resistance
- Scaling Challenges: as contact area shrinks, contact resistance increases; 20nm diameter contact has 4× higher resistance than 40nm contact even with same ρc; requires aggressive ρc reduction through interface engineering
- Silicide Thickness: thicker NiSi (15-25nm) reduces contact resistance but consumes more silicon and increases junction leakage; optimization balances resistance and junction depth
- Barrier Thickness Scaling: thinner barriers reduce series resistance but compromise diffusion blocking; 5nm TiN is minimum for reliable tungsten diffusion barrier; advanced nodes use ALD barriers for thickness control
Advanced Contact Technologies:
- Cobalt Fill: cobalt replacing tungsten at 7nm/5nm nodes; lower resistivity (6-8 μΩ·cm), better gap-fill, and eliminates fluorine contamination from WF₆; CVD Co using Co(CO)₃(NO) precursor at 200-300°C
- Ruthenium Contacts: Ru provides excellent barrier properties and low resistivity (7 μΩ·cm); can serve as combined barrier and fill metal; ALD Ru from Ru(EtCp)₂ at 250-350°C
- Contact-Over-Active-Gate (COAG): contacts land partially on gate and partially on S/D to reduce cell area; requires precise alignment and selective barrier/etch processes to prevent gate-S/D shorts
Contact formation is the most challenging interconnect process at advanced nodes — the combination of extreme aspect ratios, nanoscale dimensions, and stringent resistance requirements demands atomic-level control of etching, deposition, and planarization to achieve reliable electrical connections in billion-transistor chips.