Contact Over Active Gate (COAG) is an advanced CMOS integration technique that allows metal contacts to land directly on top of the gate electrode above the transistor active region, eliminating the traditional design rule that requires gate contacts to be placed only over the isolation (STI) region — enabling significant standard cell height reduction and area scaling that directly translates to higher logic density and lower cost per transistor.

• Conventional Limitation: In traditional layouts, the gate contact must be placed over the field oxide region outside the active area to prevent accidental shorting between the gate contact and the adjacent source/drain contacts; this restriction forces wider cells with extended gate end-caps that waste silicon area.
• COAG Benefit: By permitting gate contacts directly over the channel region, COAG eliminates one or both gate end-caps from the standard cell, reducing cell height by 1-2 contacted poly pitches (CPP); at a 48 nm CPP, this can yield 15-25 percent area reduction per cell, which compounds across billions of cells in a modern SoC.
• Self-Aligned Contact (SAC) Cap: COAG relies on a dielectric cap (typically SiN or high-k dielectric, 5-15 nm thick) deposited over the recessed metal gate after CMP; this cap provides a self-aligned etch stop that protects the gate during source/drain contact etch, preventing gate-to-contact shorts even when the contact overlaps the gate boundary.
• Contact Etch Selectivity: The source/drain contact etch must remove the ILD oxide with extremely high selectivity (greater than 20:1) to the SAC cap material; any cap erosion risks exposing the gate metal and creating a short circuit with single-digit-nanometer margin between the contact and gate.
• Gate Contact Etch: A separate gate contact etch step opens a hole through the SAC cap to reach the gate metal; this etch must stop precisely on the gate metal without penetrating through to the channel below, requiring careful endpoint control and chemistry selection.
• Multi-Contact Integration: In COAG cells, source/drain contacts and gate contacts can be in close lateral proximity, separated only by the spacer and SAC cap dielectrics; maintaining electrical isolation under worst-case overlay and CD variation demands tight statistical process control.
• Material Selection: The SAC cap material must have high etch selectivity to the ILD, low dielectric constant to minimize gate-to-contact capacitance, and sufficient thickness to provide margin against etch variation; SiN provides good selectivity but higher capacitance, while lower-k alternatives like AlO2 or SiOCN are being explored.
• Design Enablement: COAG requires updated design rules, standard cell libraries, and place-and-route tools that can exploit the new contact placement options; metal line routing over the active gate area also becomes possible, increasing routing flexibility. COAG integration is a critical enabler for continued cell height scaling at the 5 nm node and beyond, where every nanometer of area reduction has a direct impact on chip cost and competitive positioning.