Contact Over Active Gate (COAG) is a design rule advancement that allows contact plugs to be placed directly over the transistor gate, rather than requiring contacts to land only on gate extensions that project beyond the active (diffusion) region. This saves significant chip area at advanced nodes.

Traditional vs. COAG

• Traditional (Non-COAG): Contacts to the gate electrode must be placed where the gate extends beyond the active area (the gate "landing pad"). This requires the gate to be longer than the active area to provide a contact landing zone, wasting space.
• COAG: The contact can be placed anywhere along the gate, including directly above the active transistor channel. No gate extension is needed for contact landing.

Why COAG Matters

• Area Reduction: Eliminating gate extensions saves 10–15% of standard cell area at advanced nodes — a significant improvement for chip density.
• Shorter Interconnects: Contacts can be placed closer to where they're electrically needed, reducing parasitic resistance.
• Cell Height Reduction: Standard cells (the basic building blocks of digital logic) can be made shorter, improving chip density further.

How COAG Works

• At advanced nodes (7nm and below), self-aligned contact (SAC) processes deposit a protective dielectric cap (typically SiN) over the gate before forming contacts.
• When etching the contact hole, the etch chemistry is selective — it removes the interlayer dielectric (SiO₂) without attacking the SiN cap over the gate.
• For a gate contact, a separate step (contact-to-gate) opens the SiN cap precisely where the gate contact is needed.
• The self-alignment between gate cap and contact etch ensures the contact doesn't accidentally short the gate to the source/drain.

Process Challenges

• Etch Selectivity: The contact etch must have extremely high selectivity between the interlayer dielectric and the gate cap material to avoid gate exposure where not intended.
• Alignment Precision: The contact-to-gate opening must be precisely aligned — any misalignment risks shorting to adjacent source/drain contacts.
• Parasitic Capacitance: Placing contacts directly over the gate increases gate-to-contact capacitance, which can impact switching speed.

COAG is now standard practice at leading-edge nodes (5nm, 3nm, 2nm) — the area savings it provides are essential for continuing transistor density scaling as Moore's Law pushes forward.