Copper Annealing and Grain Growth is the thermal and self-driven microstructural evolution process that transforms the small-grained, high-resistance copper deposited by electroplating into large-grained, low-resistance copper through recrystallization — a phenomenon unique to electroplated copper where room-temperature self-annealing drives grain growth spontaneously over hours to days, transforming the Cu interconnect resistivity and mechanical properties without any externally applied heat. Controlling copper grain structure is critical for achieving target interconnect resistance and electromigration reliability.

Why Copper Grain Structure Matters

• Copper resistivity depends on grain boundary scattering: ρ = ρ_bulk + ρ_grain_boundary.
• Small grains → many grain boundaries → high scattering → high resistivity (5–8 µΩ·cm).
• Large grains → fewer boundaries → low scattering → near-bulk resistivity (1.7–2.5 µΩ·cm).
• Grain boundaries also provide fast diffusion paths for copper atoms → electromigration failure paths.

Self-Annealing Phenomenon

• Electroplated Cu from sulfate baths with organic additives (PEG, SPS, Cl⁻) deposits with:
• Very small grain size (10–50 nm)
• High dislocation density
• Incorporated organic inclusions (C, S from additives)
• Over 24–72 hours at room temperature: Cu grains grow spontaneously → grain size increases to 0.5–2 µm.
• Driving force: Reduction of grain boundary energy (stored strain energy from deposition).
• Result: Resistivity drops 30–50% during self-anneal (detectable in-line by 4-point probe).

Thermal Annealing to Supplement Self-Annealing

• Room temperature self-anneal is incomplete and slow → supplemented by thermal anneal.
• Typical Cu anneal: 200–400°C, 30–120 minutes in N₂ or forming gas.
• Higher T → faster, more complete grain growth → lower final resistivity.
• Constraint: Cannot exceed Cu migration temperature or delaminate low-k dielectric → 350–400°C upper limit.

Annealing Effects on Cu Microstructure

<111> Texture and Electromigration

• Thermal annealing develops strong <111> crystallographic texture (fiber texture normal to wafer).
• <111>-textured Cu has fewer grain boundaries intersecting the current flow direction → lower EM diffusivity along grain boundaries.
• Cu EM lifetime improves 2–5× with well-developed <111> texture vs. random texture.

Advanced Node Challenges

• At narrow lines (<20 nm): Cu grain size > line width → bamboo microstructure (single grain across width).
• Bamboo Cu: No continuous grain boundary path → EM limited by surface/interface diffusion, not grain boundary.
• Surface passivation (CoWP cap, MnO₂ barrier) blocks surface Cu diffusion → extends EM lifetime in bamboo regime.

In-Line Monitoring

• 4-point probe Rs measurement: Monitor Rs drop during self-anneal on wafer → confirm self-anneal completion.
• XRD: Measure Cu texture (111)/(200) ratio → characterize microstructure quality.
• TEM/EBSD: Grain size, boundary character, crystallographic orientation mapping.

Copper Annealing in Narrow Interconnects (5nm and Below)

• Line width < grain size → single-grain bamboo structure regardless of anneal.
• Anneal less impactful for grain growth (already constrained by geometry).
• Role shifts to: Remove organic inclusions from plating bath → improve Cu purity → lower resistivity.

Copper annealing and grain growth is the metallurgical foundation of reliable, low-resistance interconnects — by transforming fresh electroplated copper's chaotic microstructure into a well-textured, large-grained film, annealing bridges the gap between the resistivity of freshly deposited Cu and the near-bulk resistivity needed for the multi-kilometer total wire length in a modern high-density chip interconnect stack.