Cost Modeling

Semiconductor Manufacturing Process Cost Modeling

Overview

Semiconductor cost modeling quantifies the expenses of fabricating integrated circuits—from raw wafer to tested die. It informs technology roadmap decisions, fab investments, product pricing, and yield improvement prioritization. All dollar figures below are illustrative order-of-magnitude inputs, not quotations: tool configuration, contract terms, geography, product mix, and date can move them substantially. Replace them with program-specific data before making an investment decision.

1. Major Cost Components

1.1 Capital Equipment (40–50% of Total Cost)

This dominates leading-edge economics. A modern advanced-node fab costs $20–30 billion to construct.

Key equipment categories and approximate costs:

  • EUV lithography scanners: $150–380M each (a fab may need 15–20)
  • DUV immersion scanners: $50–80M
  • Deposition tools (CVD, PVD, ALD): $3–10M each
  • Etch systems: $3–8M each
  • Ion implanters: $5–15M
  • Metrology/inspection: $2–20M per tool
  • CMP systems: $3–5M

Capital cost allocation formula:

$$ \text{Cost per wafer pass} = \frac{\text{Tool cost} \times \text{Depreciation rate}}{\text{Throughput} \times \text{Utilization} \times \text{Uptime} \times \text{Hours/year}} $$

Where:

  • Depreciation: Typically 5–7 years
  • Utilization targets: 85–95% for expensive tools

1.2 Masks/Reticles

A complete mask set for a leading-edge process (7nm and below) costs $10–15 million or more.

EUV mask cost drivers:

  • Reflective multilayer blanks (not transmissive glass)
  • Defect-free requirements at smaller dimensions
  • Complex pellicle technology

Mask cost per die:

$$ \text{Mask cost per die} = \frac{\text{Total mask set cost}}{\text{Total production volume}} $$

1.3 Materials and Consumables (15–25%)

  • Process gases: Silane, ammonia, fluorine chemistries, noble gases
  • Chemicals: Photoresists (EUV resists are expensive), developers, CMP slurries, cleaning chemistries
  • Substrates: 300mm wafers ($100–500+ depending on spec)
  • SOI wafers: Higher cost
  • Epitaxial wafers: Additional processing cost
  • Targets/precursors: For deposition processes

1.4 Facilities (10–15%)

  • Cleanroom: Class 1 or better for critical areas
  • Ultrapure water: 18.2 MΩ·cm resistivity requirement
  • HVAC and vibration control: Critical for lithography
  • Power consumption: 100–150+ MW continuously for leading fabs
  • Waste treatment: Environmental compliance costs

1.5 Labor (10–15%)

Varies significantly by geography:

  • Direct fab operators and technicians
  • Process and equipment engineers
  • Maintenance, quality, and yield engineers

2. Yield Modeling

Yield is the most critical variable, converting wafer cost into die cost:

$$ \text{Cost per die} = \frac{\text{Cost per wafer}}{\text{Dies per wafer} \times Y} $$

Where $Y$ is the yield (fraction of good dies).

2.1 Yield Models

Poisson Model (Random Defects):

$$ Y = e^{-D_0 \times A} $$

Where:

  • $D_0$ = Defect density (defects/cm²)
  • $A$ = Die area (cm²)

Negative Binomial Model (Clustered Defects):

$$ Y = \left(1 + \frac{D_0 \times A}{\alpha}\right)^{-\alpha} $$

Where:

  • $\alpha$ = Clustering parameter (higher values approach Poisson)

Murphy's Model:

$$ Y = \left(\frac{1 - e^{-D_0 \times A}}{D_0 \times A}\right)^2 $$

2.2 Yield Components

  • Random defect yield ($Y_{\text{random}}$): Particles, contamination
  • Systematic yield ($Y_{\text{systematic}}$): Design-process interactions, hotspots
  • Parametric yield ($Y_{\text{parametric}}$): Devices failing electrical specs

Combined yield:

$$ Y_{\text{total}} = Y_{\text{random}} \times Y_{\text{systematic}} \times Y_{\text{parametric}} $$

2.3 Yield Benchmarks

  • Mature processes: 90%+ yields
  • New leading-edge: Start at 30–50%, ramp over 12–24 months

3. Dies Per Wafer Calculation

Gross dies per wafer (rectangular approximation):

$$ \text{Dies}_{\text{gross}} = \frac{\pi \times \left(\frac{D}{2}\right)^2}{A_{\text{die}}} $$

Where:

  • $D$ = Wafer diameter (mm)
  • $A_{\text{die}}$ = Die area (mm²)

More accurate formula (accounting for edge loss):

$$ \text{Dies}_{\text{good}} = \frac{\pi \times D^2}{4 \times A_{\text{die}}} - \frac{\pi \times D}{\sqrt{2 \times A_{\text{die}}}} $$

For 300mm wafer:

  • Usable area: ~70,000 mm² (after edge exclusion)

4. Cost Scaling by Technology Node

NodeWafer Cost (USD)Key Cost Drivers
28nm$3,000–4,000Mature, high yield
14/16nm$5,000–7,000FinFET transition
7nm$9,000–12,000EUV introduction (limited layers)
5nm$15,000–17,000More EUV layers
3nm$18,000–22,000GAA transistors, high EUV count
2nm$25,000+Backside power, nanosheet complexity
Wafer Cost Climbs Fastest Exactly Where EUV Layer Count Climbs each node's premium traces back to a specific process addition, not a round number technology node → wafer cost (USD) → 28nm 14/16nm 7nm 5nm 3nm 2nm $3.5k $6k $10.5k $16k $20k $25k+ a DRAM die rides the cheap end of this curve; a logic-node HBM4 base die rides the expensive end same stack, two different cost bases

4.1 Cost Per Transistor Trend

Historical Moore's Law economics:

$$ \text{Cost reduction per node} \approx 30\% $$

Current reality (sub-7nm):

$$ \text{Cost reduction per node} \approx 10\text{–}20\% $$

5. Worked Example

5.1 Assumptions

  • Wafer size: 300mm
  • Wafer cost: $15,000 (all-in manufacturing cost)
  • Die size: 100 mm²
  • Usable wafer area: ~70,000 mm²
  • Gross dies per wafer: ~680 (including partial dies)
  • Good dies per wafer: ~600 (after edge loss)
  • Yield: 85%

5.2 Calculation

Good dies:

$$ \text{Good dies} = 600 \times 0.85 = 510 $$

Cost per die:

$$ \text{Cost per die} = \frac{15{,}000}{510} \approx 29.41\ \text{USD} $$

5.3 Yield Sensitivity Analysis

YieldGood DiesCost per Die
95%570$26.32
85%510$29.41
75%450$33.33
60%360$41.67
50%300$50.00

Impact: A 25-point yield drop (85% → 60%) increases unit cost by 42%.

Cost Per Die Doesn't Rise Linearly as Yield Falls — It Compounds the same 15 denominator shrinking faster near the bottom is why a yield crisis is a cost crisis yield → cost per die (USD) → 95% → $26.32 75% → $33.33 60% → $41.67 50% → $50.00 Cost/Die = Cost/Wafer ÷ (Dies/Wafer × Y) — every point of yield lost near the bottom costs more than the point before it

6. Geographic Cost Variations

FactorTaiwan/KoreaUSEuropeChina
LaborModerateHighHighLow
PowerLow-moderateVariesHighLow
IncentivesModerateHigh (CHIPS Act)HighVery high
Supply chainDenseDevelopingLimitedDeveloping

US cost premium:

$$ \text{Premium}_{\text{US}} \approx 20\text{–}40\% $$

7. Advanced Packaging Economics

7.1 Packaging Options

  • Interposers: Silicon (expensive) vs. organic (cheaper)
  • Bonding: Hybrid bonding enables fine pitch but has yield challenges
  • Technologies: CoWoS, InFO, EMIB (each with different cost structures)

7.2 Compound Yield

For chiplet architectures with $N$ dies:

$$ Y_{\text{package}} = \prod_{i=1}^{N} Y_i $$

Example (N = 4 chiplets, each 95% yield):

$$ Y_{\text{package}} = 0.95^4 = 0.814 = 81.4\% $$

8. Cost Modeling Methodologies

8.1 Activity-Based Costing (ABC)

Maps costs to specific process operations, then aggregates:

$$ \text{Total Cost} = \sum_{i=1}^{n} (\text{Activity}_i \times \text{Cost Driver}_i) $$

8.2 Process-Based Cost Modeling (PBCM)

Links technical parameters to equipment requirements:

$$ \text{Cost} = f(\text{deposition rate}, \text{etch selectivity}, \text{throughput}, ...) $$

8.3 Learning Curve Model

Cost reduction with cumulative production:

$$ C_n = C_1 \times n^{-b} $$

Where:

  • $C_n$ = Cost of the $n$-th unit
  • $C_1$ = Cost of the first unit
  • $b$ = Learning exponent (typically 0.1–0.3 for semiconductors)

9. Key Cost Metrics Summary

MetricFormula
Cost per Wafer$\sum \text{(CapEx + OpEx + Materials + Labor + Facilities)}$
Cost per Die$\frac{\text{Cost per Wafer}}{\text{Dies per Wafer} \times \text{Yield}}$
Cost per Transistor$\frac{\text{Cost per Die}}{\text{Transistors per Die}}$
Cost per mm²$\frac{\text{Cost per Wafer}}{\text{Usable Wafer Area} \times \text{Yield}}$

10. Industry Cost Drivers

1. EUV cost trajectory: Layer count, scanner configuration, throughput, uptime, resist, masks, and inspection all influence lithography cost per good wafer
2. Sustainability costs: Carbon neutrality requirements, water recycling mandates
3. Supply chain reshoring: Government subsidies changing cost calculus
4. 3D integration: Shifts cost from transistor scaling to packaging
5. Mature-node utilization: Loading and product mix can change depreciation absorption and therefore cost per wafer

11. HBM4 Stack Economics

An HBM4 stack is a staged cost model, not one wafer-cost calculation multiplied by a blanket compound-yield term. DRAM and base dies first pass wafer sort and become known-good dies (KGDs), so their procurement or transfer costs already include their respective wafer yields. Those screened inputs then enter thinning, bonding, molding, package integration, burn-in, and final test. Assembly yield belongs in this second stage. Charging raw-die yield again in the assembly denominator double-counts the same loss.

HBM4 economics: follow the physical flow of value at risk Known-good-die screening and stack assembly are separate yield gates; model them separately. STAGE 1 · CREATE SCREENED INPUTS DRAM wafers wafer cost ÷ good dies + probe, thinning, handling unit input: CDRAM,KGD Base-die wafers independent process flow and wafer-sort yield unit input: CBASE,KGD Screening boundary KGD price already embeds wafer yield and probe escapes do not divide by them again STAGE 2 · ASSEMBLE, TEST, AND SHIP N screened DRAM+ one screened base die Stack assembly bond + inspect each tier mold, debond, package yield gate: YASM Final test speed / power bin repair + burn-in yield: YFT shipped Expected cost per shipped stack CSHIP = [N·CDRAM,KGD + CBASE,KGD + CASM] / YASM + CPKG+FT/YFT Use a stage-resolved model when failures occur after value has been added; allocate rework and salvage at the stage where they actually occur. Sensitivity that deserves attention ∂CSHIP/∂YASM = −CAT RISK/YASM² Late loss destroys embedded value. Prioritize dollars recovered.

The useful denominator is therefore delivered good stacks, not the product of every historical die yield. If independent per-tier assembly survival is $p$, a first-pass estimate is $Y_{\text{ASM}} \approx p^N$; real data may depart from that estimate because defects can be correlated by wafer, tool, bond interface, or handling event. Redundancy, repair, binning, rework, and salvage also change the result. Report those assumptions explicitly, then divide by usable shipped capacity to obtain cost per delivered bit. The practical lesson is economic as much as statistical: preventing a late failure protects every dollar already embedded in the stack.

Reference Formulas

Yield Models

Poisson:           Y = exp(-D₀ × A)
Negative Binomial: Y = (1 + D₀×A/α)^(-α)
Murphy:            Y = ((1 - exp(-D₀×A)) / (D₀×A))²

Cost Equations

Cost/Die     = Cost/Wafer ÷ (Dies/Wafer × Yield)
Cost/Wafer   = CapEx + Materials + Labor + Facilities + Overhead
CapEx/Pass   = (Tool Cost × Depreciation) ÷ (Throughput × Util × Uptime × Hours)

Dies Per Wafer

Gross Dies ≈ π × (D/2)² ÷ A_die
Net Dies   ≈ (π × D²)/(4 × A_die) - (π × D)/√(2 × A_die)

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