CoWoS technology. is TSMC’s Chip-on-Wafer-on-Substrate family for integrating logic dies, chiplets, and high-bandwidth memory in large 2.5D packages. In the canonical CoWoS-S structure, top dies are attached to a passive silicon interposer with dense wiring and TSVs; that chip-on-wafer assembly is then mounted on an organic package substrate. The resulting short, wide memory links are foundational for high-performance computing and AI accelerator modules. Packaging is a coupled electrical, mechanical, thermal, manufacturing, and economic system. Interconnect geometry sets resistance, inductance, capacitance, crosstalk, return paths, and maximum practical data rate. Materials with different coefficients of thermal expansion create stress during assembly, board reflow, power cycling, storage, and field operation. Heat must cross interfaces, attach layers, spreaders, substrates, lids, thermal interface materials, boards, and coolers without exceeding junction or memory limits. Moisture, mobile ions, particles, corrosion, delamination, voids, cracks, electromigration, solder fatigue, and warpage can turn a locally acceptable structure into an unreliable product.
Architecture, methods, and economic choices. CoWoS is a family rather than one cross-section. CoWoS-S uses a silicon interposer and supports the highest-density routing and integrated capacitor options. CoWoS-R uses an RDL interposer based on polymer and copper. CoWoS-L combines an RDL interposer with local silicon interconnect structures where fine wiring is needed. TSMC recommends R or L for very large interposer sizes beyond the stated CoWoS-S range; exact availability is generation and customer specific. Cost depends on die yield, known-good-die confidence, interconnect pitch, layer count, substrate or interposer area, reticle stitching, carrier cycles, bond yield, stack yield, underfill and molding, test time, repair or rework options, capital utilization, cycle time, and supply concentration. Yield compounds across multiple dies and interfaces, so redundancy, repair, binning, partial-good configurations, and test insertion points matter. Advanced packages can improve system cost by using chiplets and heterogeneous nodes even when package cost rises. Procurement must consider capacity, tooling ownership, material lead time, geographic resilience, process-change notice, lifecycle, and recovery plans.
Process integration and package co-design. Assembly includes known-good accelerator and HBM selection, interposer fabrication and test, fine-pitch chip attach, underfill or molding, wafer-level handling, interposer TSV and bump connection, organic substrate attach, lid and thermal integration, ball attach, and system test. The package must deliver enormous HBM bandwidth, chiplet links, current, clock quality, and heat removal across a body much larger than conventional mobile packages. Co-design starts from die floorplan, bump map, power domains, memory topology, signal escape, clocking, package stackup, board stackup, voltage regulation, cooling, test access, mechanical keep-outs, and assembly rules. Power-delivery impedance and simultaneous switching noise can constrain compute before transistor capability does. High-speed channels require package and board models with connectors, vias, discontinuities, and return paths. Thermal simulations need realistic interface resistance, heat-source maps, lid bow, coolant boundary conditions, and workload transients. Mechanical models address warpage, die stress, solder strain, underfill, board bending, and handling.
Manufacturing control, failure mechanisms, and reliability. CoWoS capacity includes more than silicon-interposer wafers: it depends on HBM, advanced substrates, bumping and bond tools, carriers, underfill, molding, test, lids, thermal materials, and qualified assembly lines. A single weak yield or capacity link constrains modules. Large interposers and substrates introduce reticle stitching, warpage, stress, power drop, signal escape, thermal gradients, and board-assembly risk. Product claims about a particular GPU package should be tied to exact generation and supplier disclosure. A production flow begins with known-good wafers or dies, incoming inspection, temporary carriers where required, thinning, singulation or reconstitution, surface preparation, alignment, attach or bond, interconnect formation, underfill or molding, cure, lid or heat-spreader integration, ball attach, singulation, marking, inspection, electrical test, burn-in or stress screens where justified, and board-level qualification. Each step changes the next step’s alignment, cleanliness, topography, stress, thermal history, and yield. Process windows must be demonstrated at wafer center and edge, across die size and pattern density, after tool maintenance, and through allowed material-lot variation.
| CoWoS member | Intermediate structure | Density / size direction | Primary advantage | Primary trade-off |
|---|---|---|---|---|
| CoWoS-S | Full silicon interposer with TSVs | Highest fine wiring; public platform up to 3.3-reticle class | Maximum bandwidth density and integrated capacitor options | Silicon area, cost and size scaling |
| CoWoS-R | Polymer and copper RDL interposer | Larger flexible RDL structures | Area scaling and joint-compliance potential | Coarser than full silicon; polymer behavior |
| CoWoS-L | RDL interposer plus local silicon interconnect | Fine local links with large package scaling | Places silicon only where density is needed | Bridge / RDL integration complexity |
| Package selection | Exact customer generation | Platform and capacity specific | Matches bandwidth, body size and cost | Names alone do not specify implementation |
<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">CoWoS: TSMC's Chip-on-Wafer-on-Substrate 2.5D platform</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Top dies on a silicon interposer, on an organic substrate — the short, wide HBM links behind AI accelerators</text><!-- ===== PANEL 1: decode the name ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#38bdf8" font-size="12" font-weight="700">1 · The name is the recipe</text><text x="70" y="120" fill="#8b949e" font-size="7" text-anchor="middle">HBM</text><text x="188" y="120" fill="#8b949e" font-size="7" text-anchor="middle">HBM</text><g stroke="#6f6f6a" stroke-width="0.5" fill="#4a5a72"><rect x="50" y="124" width="38" height="6"/><rect x="50" y="131" width="38" height="6"/><rect x="50" y="138" width="38" height="6"/><rect x="50" y="145" width="38" height="6"/></g><g stroke="#6f6f6a" stroke-width="0.5" fill="#4a5a72"><rect x="170" y="124" width="38" height="6"/><rect x="170" y="131" width="38" height="6"/><rect x="170" y="138" width="38" height="6"/><rect x="170" y="145" width="38" height="6"/></g><rect x="98" y="122" width="60" height="29" fill="#38506a" stroke="#6f8fb0"/><text x="128" y="140" fill="#dbe7f3" font-size="8" text-anchor="middle">logic / GPU</text><g fill="#e0b13a"><circle cx="60" cy="155" r="1.8"/><circle cx="72" cy="155" r="1.8"/><circle cx="108" cy="155" r="1.8"/><circle cx="124" cy="155" r="1.8"/><circle cx="140" cy="155" r="1.8"/><circle cx="180" cy="155" r="1.8"/><circle cx="192" cy="155" r="1.8"/></g><rect x="42" y="158" width="180" height="20" fill="#2b2f36" stroke="#6f6f6a"/><text x="132" y="171" fill="#c9d1d9" font-size="7.5" text-anchor="middle">silicon interposer + TSVs</text><g stroke="#b8732e" stroke-width="1.5"><line x1="70" y1="158" x2="70" y2="178"/><line x1="132" y1="158" x2="132" y2="178"/><line x1="192" y1="158" x2="192" y2="178"/></g><g fill="#c98a2e"><circle cx="66" cy="182" r="2.6"/><circle cx="100" cy="182" r="2.6"/><circle cx="132" cy="182" r="2.6"/><circle cx="164" cy="182" r="2.6"/><circle cx="198" cy="182" r="2.6"/></g><rect x="42" y="186" width="180" height="20" fill="#5a4632" stroke="#6f6f6a"/><text x="132" y="199" fill="#e8d9c5" font-size="7.5" text-anchor="middle">organic package substrate</text><g fill="#c98a2e"><circle cx="60" cy="210" r="3"/><circle cx="96" cy="210" r="3"/><circle cx="132" cy="210" r="3"/><circle cx="168" cy="210" r="3"/><circle cx="204" cy="210" r="3"/></g><text x="32" y="234" font-size="9" font-weight="700"><tspan fill="#e0b13a">Chip</tspan><tspan fill="#8b949e"> -on- </tspan><tspan fill="#38bdf8">Wafer</tspan><tspan fill="#8b949e"> -on- </tspan><tspan fill="#7ee6c0">Substrate</tspan></text><text x="32" y="252" fill="#adb5bd" font-size="8.4">Dies are attached to a silicon interposer</text><text x="32" y="264" fill="#adb5bd" font-size="8.4">(chip-on-wafer), then that assembly mounts</text><text x="32" y="276" fill="#adb5bd" font-size="8.4">on an organic substrate (on-substrate).</text><text x="32" y="298" fill="#38bdf8" font-size="8.6" font-weight="600">Short, wide links feed HBM to the logic die.</text><text x="32" y="320" fill="#8b949e" font-size="8.3">TSMC's 2.5D platform, in volume since 2012;</text><text x="32" y="332" fill="#8b949e" font-size="8.3">package bodies now span several reticles.</text><!-- ===== PANEL 2: the family ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#a99cf0" font-size="12" font-weight="700">2 · One family, three interposers</text><text x="279" y="115" fill="#7ee6c0" font-size="9.5" font-weight="700">CoWoS-S</text><rect x="342" y="106" width="54" height="11" fill="#2b2f36" stroke="#6f6f6a"/><text x="424" y="115" fill="#8b949e" font-size="7.4">silicon</text><text x="279" y="128" fill="#adb5bd" font-size="7.8">full silicon interposer — highest density + caps</text><text x="279" y="150" fill="#9fd8ef" font-size="9.5" font-weight="700">CoWoS-R</text><rect x="342" y="141" width="54" height="11" fill="#3d3348" stroke="#6f6f6a"/><g stroke="#b8732e" stroke-width="0.7"><line x1="344" y1="145" x2="394" y2="145"/><line x1="344" y1="148" x2="394" y2="148"/></g><text x="424" y="150" fill="#8b949e" font-size="7.4">RDL</text><text x="279" y="163" fill="#adb5bd" font-size="7.8">polymer + copper RDL — scales to larger bodies</text><text x="279" y="185" fill="#e0b13a" font-size="9.5" font-weight="700">CoWoS-L</text><rect x="342" y="176" width="54" height="11" fill="#3d3348" stroke="#6f6f6a"/><rect x="352" y="178" width="10" height="7" fill="#b8732e"/><rect x="376" y="178" width="10" height="7" fill="#b8732e"/><text x="424" y="185" fill="#8b949e" font-size="7.4">RDL+Si</text><text x="279" y="198" fill="#adb5bd" font-size="7.8">RDL + local silicon bridges — fine where needed</text><line x1="279" y1="212" x2="481" y2="212" stroke="#30363d" stroke-width="1"/><text x="279" y="231" fill="#adb5bd" font-size="8.5">All three are chip-on-wafer-on-substrate;</text><text x="279" y="243" fill="#adb5bd" font-size="8.5">only the middle interposer differs.</text><text x="279" y="263" fill="#a99cf0" font-size="8.6" font-weight="600">Pick the interposer for size vs density.</text><rect x="279" y="278" width="202" height="70" rx="6" fill="#111a24" stroke="#30363d"/><text x="291" y="296" fill="#e6edf3" font-size="9" font-weight="700">Why a family?</text><text x="291" y="312" fill="#adb5bd" font-size="8.2">A full silicon interposer gets costly and</text><text x="291" y="324" fill="#adb5bd" font-size="8.2">hard to yield past a few reticles — so R</text><text x="291" y="336" fill="#adb5bd" font-size="8.2">and L trade some density for much larger,</text><text x="291" y="348" fill="#adb5bd" font-size="8.2">cheaper package bodies.</text><!-- ===== PANEL 3: why + hard parts ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#34d399" font-size="12" font-weight="700">3 · Why it's the AI platform</text><text x="526" y="108" fill="#e6edf3" font-size="10" font-weight="700">Short, wide HBM links</text><text x="526" y="126" fill="#adb5bd" font-size="8.6">A large logic die flanked by HBM stacks</text><text x="526" y="138" fill="#adb5bd" font-size="8.6">on one interposer delivers the enormous,</text><text x="526" y="150" fill="#adb5bd" font-size="8.6">low-energy memory bandwidth that AI</text><text x="526" y="162" fill="#adb5bd" font-size="8.6">accelerators need.</text><text x="526" y="184" fill="#34d399" font-size="8.6" font-weight="600">The default 2.5D platform for GPUs.</text><line x1="526" y1="198" x2="728" y2="198" stroke="#30363d" stroke-width="1"/><text x="526" y="217" fill="#f87171" font-size="10" font-weight="700">The hard parts</text><text x="526" y="235" fill="#adb5bd" font-size="8.6">Capacity is a chain: HBM, substrates,</text><text x="526" y="247" fill="#adb5bd" font-size="8.6">bumping, carriers, underfill, test, lids —</text><text x="526" y="259" fill="#adb5bd" font-size="8.6">one weak link caps module supply.</text><text x="526" y="277" fill="#adb5bd" font-size="8.6">Large interposers add reticle stitching,</text><text x="526" y="289" fill="#adb5bd" font-size="8.6">warpage, stress, power drop, and</text><text x="526" y="301" fill="#adb5bd" font-size="8.6">thermal gradients across a huge body.</text><text x="526" y="323" fill="#f87171" font-size="8.6" font-weight="600">Packaging capacity gates AI supply.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="404" fill="#38bdf8" font-size="10.5" font-weight="700">Chip-on-Wafer-on-Substrate</text><text x="32" y="421" fill="#adb5bd" font-size="8.7">Dies on a silicon interposer (chip-on-</text><text x="32" y="434" fill="#adb5bd" font-size="8.7">wafer), mounted on an organic substrate</text><text x="32" y="447" fill="#adb5bd" font-size="8.7">— the three tiers the acronym names.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="404" fill="#a99cf0" font-size="10.5" font-weight="700">S / R / L</text><text x="279" y="421" fill="#adb5bd" font-size="8.7">Full silicon (density), polymer RDL (area),</text><text x="279" y="434" fill="#adb5bd" font-size="8.7">or RDL + local silicon bridges — three</text><text x="279" y="447" fill="#adb5bd" font-size="8.7">interposers under one platform.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="404" fill="#f87171" font-size="10.5" font-weight="700">Capacity is a chain</text><text x="526" y="421" fill="#adb5bd" font-size="8.7">More than interposer wafers: HBM, tools,</text><text x="526" y="434" fill="#adb5bd" font-size="8.7">substrates and test all gate output —</text><text x="526" y="447" fill="#adb5bd" font-size="8.7">CoWoS supply is an AI bottleneck.</text></svg>
Qualification, selection, and CFS connection. TSMC states that CoWoS entered volume production in 2012 and its current public platform material distinguishes S, R, and L. Selection should compare routed density, interposer size, die count, HBM generation, power delivery, thermal solution, package and board size, test strategy, capacity, and cost. CoWoS is a manufacturing platform; accelerator performance still depends on architecture, memory, network, software, cooling, and workload. Qualification combines construction analysis, acoustic microscopy, X-ray and computed tomography, cross-sectioning, scanning electron microscopy, surface and film metrology, shear or pull tests, warpage, electrical continuity, daisy chains, high-speed characterization, thermal resistance, temperature cycling, power cycling, humidity bias, high-temperature storage, drop or vibration where applicable, and accelerated-life models. Sample plans distinguish process development, characterization, qualification, production control, and failure analysis. A passing package-level test does not prove board reliability, and an accelerated test is useful only when its failure mechanism matches field physics. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.
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