Cryogenic etching is a continuous deep reactive-ion etch that holds a silicon wafer near −80 to −120 °C while an $ ext{SF}_6/ ext{O}_2$ plasma cuts smooth, nearly vertical, high-aspect-ratio features. Fluorine radicals supplied by $ ext{SF}_6$ react with silicon to form volatile $ ext{SiF}_4$, while oxygen builds a nanometer-scale silicon oxyfluoride ($ ext{SiO}_x ext{F}_y$) film on cold surfaces. Directional ions remove that film from the trench floor but leave it on the sidewalls. Etch and passivation therefore happen at the same time: the bottom stays chemically active, the walls stay protected, and the profile advances downward without the periodic scallops of a pulsed Bosch process.

Low temperature is an active process variable, not merely a cooling precaution. The protective oxyfluoride is stable only while the surface is cold. If the wafer warms, the film thins or desorbs, lateral fluorine attack increases, and the trench can bow or undercut. A cryogenic tool therefore couples a chilled electrostatic chuck to backside helium, a temperature-controlled coolant loop, and tight wafer-to-chuck contact. Local plasma heat load, helium leakage, backside particles, wafer bow, and edge-clamp geometry can all turn into across-wafer profile variation. Temperature must be measured and controlled as deliberately as pressure or RF power.

The chemistry is a three-flux balance. Fluorine-radical flux sets the available silicon reaction rate; oxygen flux and surface temperature set the strength of the $ ext{SiO}_x ext{F}_y$ wall film; ion energy and angular spread decide where that film is cleared. Too little oxygen, too much platen bias, or a wafer that is too warm produces lateral etching and re-entrant walls. Too much oxygen, insufficient ion energy, or an overly cold surface can pinch the opening, taper the trench, or stop the etch. Source power controls plasma density, platen power controls ion energy, chamber pressure shapes ion scattering, and total flow controls residence time and byproduct removal. These knobs interact, so a recipe is a process window rather than a list of independent setpoints.

Smooth walls are the main reason to choose cryogenic DRIE. A Bosch trench records every alternating etch/passivation cycle as a scallop; cryogenic etching uses continuous protection and can produce much lower sidewall roughness. That matters when the wall itself is functional: optical waveguides and resonators lose light to roughness, microfluidic channels need predictable surfaces, and MEMS flexures and inertial structures benefit from controlled dimensions and reduced stress concentration. Cryogenic DRIE can also deliver high aspect ratio and high silicon etch rate, but the attainable depth still depends on feature width, mask opening, transport, and thermal uniformity.

Aspect-ratio-dependent etching still applies. As a trench deepens, neutral reactants have a harder path to the floor, byproducts escape more slowly, and ions are shadowed or deflected. Narrow openings therefore etch more slowly than wide ones, creating depth differences across a layout. Charging near an insulating stop layer can cause footing or notching; mask erosion changes the critical dimension; and angular ions can produce bowing or microtrenching. Dummy features, density-aware layout, pressure and bias tuning, endpoint strategy, and calibrated over-etch all remain necessary even when the sidewall chemistry is smooth.

Mask and materials choices become more demanding at cryogenic temperature. Photoresist may crack, harden, or lose adhesion under thermal stress, while oxide, nitride, or metal hard masks offer better selectivity but add deposition and removal steps. Condensation and chamber moisture must be controlled during cooldown and warmup. The oxyfluoride passivation is intentionally transient: after the wafer returns toward room temperature it desorbs or is removed in the clean sequence, which avoids the thick fluorocarbon residue associated with Bosch processing but makes warmup discipline part of the recipe.

A useful qualification plan separates profile, rate, and damage. Cross-section SEM should measure top, middle, and bottom critical dimension, sidewall angle, bow, microtrenching, scallop-equivalent roughness, mask loss, and depth across feature widths and pattern densities. Blanket and patterned wafers should map etch rate and uniformity. Optical emission or interferometry can support endpoint control, while post-etch surface analysis checks oxygen/fluorine residue. Electrical or mechanical structures then reveal plasma damage, charging, stiction, or strength loss that a visually straight trench can hide.

Choose cryogenic etching when smoothness is worth the thermal complexity. It is especially compelling for silicon photonics, optical MEMS, high-Q resonators, precision inertial sensors, microfluidics, and research structures whose sidewalls affect performance. Choose Bosch when maximum depth, throughput, mature hardware, and a wide manufacturing base matter more than scallops. The two methods solve the same anisotropy problem with different clocks: Bosch alternates protection and removal in time; cryogenic DRIE balances them continuously on a cold surface.

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  <text x="380" y="458" fill="#6b7684" font-size="11" text-anchor="middle">Bosch alternates protection and etch in time; cryogenic DRIE balances both continuously by keeping the silicon cold.</text>
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Following cryogenic etching from plasma chemistry through chuck thermals, profile metrology, and device performance is exactly the cross-domain process view Chip Foundry Services is built to provide—connecting a smooth sidewall on an SEM image to the equipment controls and silicon behavior that created it.