CUDA Tensor Operations and cuBLAS is the NVIDIA GPU library ecosystem for high-performance linear algebra and tensor computation — providing highly optimized implementations of matrix multiplication (GEMM), convolution, and tensor contractions that form the computational backbone of deep learning training and inference, scientific simulation, and numerical computing. cuBLAS and its extensions (cuBLASLt, cuDNN, cuTENSOR) achieve near-theoretical-peak GPU performance by exploiting Tensor Cores, memory hierarchy, and instruction-level parallelism.

Why GEMM Is Central

• Matrix multiplication (GEMM: C = α×A×B + β×C) accounts for 70–90% of FLOPs in deep learning.
• Fully connected layers: Weight matrix × activation matrix → GEMM.
• Attention mechanism: Q×K^T → GEMM; Attention×V → GEMM.
• Convolution: Implicit GEMM — convert conv to matrix multiply via im2col.
• Consequence: Optimizing GEMM throughput ≈ optimizing overall model throughput.

NVIDIA Tensor Cores

• Dedicated matrix multiply units introduced in Volta (V100): 4×4 matrix × 4×4 matrix in one instruction.
• Each Tensor Core: 64 FP16 FMAs per clock → 128 FLOPs/clock.
• H100 GPU: 528 Tensor Cores × 2 GHz × 256 FLOPs = ~270 TFLOPS (FP16 theoretical).
• Tensor Core precision: FP16, BF16, FP8, INT8, INT4 → different datatypes for training vs. inference.

cuBLAS API

// Single-precision GEMM: C = A × B
cublasHandle_t handle;
cublasCreate(&handle);

cublasSgemm(handle,
    CUBLAS_OP_N, CUBLAS_OP_N, // no transpose
    M, N, K,                   // dimensions
    &alpha,                     // scalar
    d_A, M,                    // matrix A (device)
    d_B, K,                    // matrix B (device)
    &beta,
    d_C, M);                   // output C (device)

cuBLASLt (LightWeight cuBLAS)

• More flexible GEMM interface for Tensor Core operations.
• Supports: Mixed precision (FP16 in, FP32 accumulate), epilogue fusion (ReLU, bias add after GEMM).
• Algorithm search: cublasLtMatmulAlgoGetIds() → enumerate algorithms → benchmark → pick fastest.
• Used by: PyTorch F.linear(), cuDNN attention layers, TensorRT.

cuTENSOR

• General tensor contraction library (beyond 2D matrix multiply).
• C[i,j,k] = A[i,m,n] × B[m,n,j,k] — arbitrary tensor index contraction.
• Used for: Tensor network simulation, multi-dimensional convolution, quantum chemistry.

Memory Hierarchy Optimization

• GEMM tiles: Partition A, B into tiles that fit in L1/shared memory → reduce global memory traffic.
• Tiling hierarchy: Thread block tile (fits in shared memory) → Warp tile (fits in registers) → Thread tile.
• Shared memory double buffering: Load next tile while computing current tile → hide memory latency.
• Memory layout: Row-major vs. column-major matters for coalescing → cuBLAS handles transparently.

FP8 GEMM (H100 Feature)

• H100 Hopper: FP8 Tensor Core → 2× throughput vs. FP16 at same precision level.
• Training: Use FP8 for forward pass GEMM → FP32 accumulation → FP8 gradient → ~2× faster.
• cuBLASLt FP8 GEMM: E4M3 and E5M2 formats supported.
• Scaling: Dynamic loss scaling required to prevent underflow in FP8 gradient range.

Batched GEMM

• Many independent small GEMMs in parallel: Batch of B matrices.
• Example: Attention heads in transformer — B = batch_size × num_heads independent QK^T GEMMs.
• cublasSgemmBatched(): Array of matrix pointers → launch B GEMMs in one call.
• Strided batched: cublasSgemmStridedBatched() → matrices contiguous in memory → faster.

Flash Attention vs. cuBLAS GEMM

• Standard attention: 3 separate GEMM calls → intermediate matrices in global memory → memory bound.
• Flash Attention: Fused kernel → computes Q×K^T + softmax + ×V in one pass → no global write of attention matrix.
• Flash Attention implementation uses CUDA directly, not cuBLAS → custom tiling for SRAM.

CUDA tensor operations and cuBLAS are the computational engine underneath every major AI framework — when PyTorch, TensorFlow, or JAX run a matrix multiplication, they invoke cuBLAS at the lowest level, making cuBLAS performance optimization directly equivalent to optimizing the throughput of every neural network trained or deployed on NVIDIA hardware, which encompasses the vast majority of AI computation worldwide.