Compute Express Link (CXL) is the open industry interconnect standard built on PCIe physical layer that provides cache-coherent memory access between CPUs and attached devices (accelerators, memory expanders, smart NICs) — enabling a unified memory space where the CPU and devices can access each other's memory with hardware cache coherence, eliminating the explicit memory copy and synchronization overhead that dominates CPU-GPU data transfer in discrete accelerator architectures.

CXL Protocol Types

• CXL.io: PCIe-compatible I/O protocol for device discovery, configuration, and DMA. Equivalent to standard PCIe enumeration and data transfer.
• CXL.cache: Allows the device to cache host CPU memory with full hardware coherence. The device's cache participates in the CPU's coherence protocol (snoop/invalidation). Accelerators can read/write CPU memory at cache-line granularity without software coherence management.
• CXL.mem: Allows the CPU to access device-attached memory as if it were local DRAM. The memory appears on the CPU's physical address map. Load/store instructions directly access CXL-attached memory — no explicit DMA or memcpy needed.

CXL Device Types

Memory Pooling and Disaggregation

CXL 2.0/3.0 enables memory pooling — a shared CXL memory device (Type 3) connected to multiple hosts via a CXL switch. Hosts can dynamically allocate memory from the pool as needed:

• Capacity Scaling: Add memory beyond what DIMM slots allow. A server with 512 GB local DRAM can access an additional 2 TB via CXL.
• Stranded Memory Recovery: In heterogeneous clusters, some servers run memory-hungry workloads while others have idle DRAM. Pooling allows underutilized memory to be reallocated dynamically.
• Tiered Memory: CXL memory as a slower (higher-latency) but larger memory tier. The OS or application transparently places hot pages in local DRAM and cold pages in CXL memory.

Performance Characteristics

• Bandwidth: CXL 3.0 over PCIe 6.0: 64 GT/s × 16 lanes = 128 GB/s (bidirectional). Comparable to one DDR5 channel.
• Latency: CXL.mem access adds ~80-150 ns over local DRAM (~80 ns). Total: ~160-230 ns. Similar to remote NUMA access in 2-socket systems.
• Cache Coherence: Hardware-managed. No software overhead for maintaining coherence between CPU and CXL device caches.

Impact on Parallel Computing

CXL enables CPU-accelerator memory sharing without explicit data transfer — the CPU and GPU can operate on the same data simultaneously with hardware coherence. This eliminates the PCIe memcpy bottleneck that adds milliseconds of overhead per data exchange in current discrete GPU systems.

CXL is the interconnect technology that dissolves the boundary between CPU and accelerator memory — creating unified, coherent memory spaces that simplify programming, reduce data movement overhead, and enable flexible memory capacity scaling across heterogeneous computing systems.