Dataflow Processor Architecture: Spatial Computing via Coarse-Grained Reconfigurable Arrays — compute elements directly mapped to hardware nodes with data-driven execution model eliminating control-flow bottlenecks

Dataflow Execution Model

• Data-Driven Execution: compute triggered when all operands available (vs instruction fetch in von Neumann), tokens flowing through dataflow graph
• Spatial Architecture: computation parallelism directly expressed in hardware mapping (no instruction sequencing overhead)
• Zero Idle Computation: firing rule ensures only enabled nodes execute, reducing power vs GPU/CPU

Coarse-Grained Reconfigurable Array (CGRA)

• Processing Elements (PEs): 100s-1000s of compute nodes, each with local memory and arithmetic units
• Interconnect Fabric: mesh or torus topology for PE communication, high bandwidth internal network
• Reconfigurability: configuration bits specify PE function + interconnect routing for different algorithms

Prominent Dataflow Architectures

• Cerebras Wafer Scale Engine (WSE-3): 850,000 AI cores on single wafer, 2.6 trillion transistors, 120 PB/s internal bandwidth, spatial fabric
• SambaNova RDU (Reconfigurable Data Unit): 50 TB/s bandwidth, hierarchical memory (L0-L2), ideal for graph analytics + ML
• Groq TSP (Tensor Streaming Processor): 60 TB/s I/O bandwidth, instruction-synchronous execution, stream dataflow programming model

Dataflow vs Von Neumann Control Flow

• Von Neumann Bottleneck: fetch-decode-execute cycle, instruction memory bandwidth limits throughput
• Dataflow Advantage: parallelism exploitation, reduced instruction overhead, energy efficiency (no speculative execution waste)
• Trade-off: less flexible for irregular workloads (sparse, dynamic control)

Programming and Applications

• Streaming Dataflow Graphs: define DAG of operations + data dependencies, compiler maps to CGRA
• Optimal for: neural networks (dense computations), signal processing, analytics (graph algorithms)
• Challenges: compiler complexity, limited tooling maturity vs CUDA/OpenMP

Future Direction: spatial architectures expected to dominate as power limits prevent traditional CPU/GPU frequency scaling, dataflow execution model matches workload parallelism naturally.