Decoupling capacitors (decaps) are capacitors placed on the die (or in the package) to stabilize the power supply by supplying instantaneous current during switching transients — preventing excessive dynamic voltage drop (IR drop) that would cause timing failures or functional errors.
Why Decoupling Capacitors Are Needed
- When digital circuits switch, they draw large, brief current pulses from the power supply.
- The power grid has inductance (from package bond wires, bumps, and traces) and resistance (from on-die metal).
- Inductance prevents the power supply from responding instantly: $V = L \frac{dI}{dt}$ — fast current changes cause voltage droops.
- Decoupling capacitors act as local charge reservoirs — they supply current immediately during switching, before the slower package-level supply can respond.
How Decaps Work
- A charged capacitor between VDD and VSS supplies current when VDD droops: $I = C \frac{dV}{dt}$.
- The capacitor charges during idle periods and discharges during switching — smoothing the voltage ripple.
- Multiple levels of decoupling provide coverage across different frequency ranges.
Decoupling Hierarchy
| Level | Location | Capacitance | Frequency Range |
|-------|----------|-------------|----------------|
| On-Die | Within the chip | pF–nF | >100 MHz (highest frequency) |
| Package | In package substrate | nF–µF | 10–100 MHz |
| PCB | On the circuit board | µF–mF | <10 MHz |
| VRM | Voltage regulator | mF | DC–kHz |
On-Die Decoupling Capacitor Types
- MOS Decap: A MOS transistor with gate connected to VDD and source/drain to VSS (or vice versa). Uses gate oxide capacitance. Most common — fabricated with no additional process cost.
- MIM (Metal-Insulator-Metal) Decap: Parallel plate capacitor in the metal stack. Higher capacitance density but requires additional mask layers.
- MOM (Metal-Oxide-Metal) Decap: Interdigitated metal fingers using fringe capacitance. No extra process cost, moderate density.
- Deep Trench Decap: High-AR trench filled with dielectric and conductor — very high capacitance density, used in DRAM/advanced logic.
Placement Strategy
- Near High-Activity Blocks: Place decaps close to blocks with high switching activity — CPU cores, clock distribution, I/O drivers.
- Fill Empty Space: Use decap filler cells in unused areas of the standard cell layout.
- Distributed: Spread decaps throughout the die rather than concentrating them — effective frequency response depends on proximity.
Design Considerations
- Leakage: MOS decaps (especially thin-oxide) leak current — adding decaps increases static power. Use thick-oxide decaps where possible.
- Area: Decaps consume die area — typically 5–15% of core area.
- Resonance: The decap network combined with package inductance creates an LC resonant circuit — target impedance at the resonant frequency must be managed.
Decoupling capacitors are essential for power integrity — without adequate on-die decoupling, modern high-performance chips would experience unacceptable voltage noise during operation.