Deep Reactive Ion Etching (DRIE) for TSV is the plasma-based silicon etching process that creates the high-aspect-ratio vertical holes required for through-silicon vias — using alternating etch and passivation cycles (the Bosch process) to achieve near-vertical sidewalls at depths of 50-200 μm with aspect ratios up to 20:1, forming the physical cavities that will be lined, seeded, and filled with copper to create the vertical electrical interconnects in 3D integrated circuits.

What Is DRIE for TSV?

• Definition: A specialized reactive ion etching technique optimized for etching deep, narrow holes in silicon with vertical sidewall profiles — the critical first step in TSV fabrication that defines the via geometry (diameter, depth, profile, sidewall quality).
• Bosch Process: The dominant DRIE technique — rapidly alternates between an isotropic SF₆ etch step (1-5 seconds, removes silicon) and a C₄F₈ passivation step (1-3 seconds, deposits a fluorocarbon polymer on all surfaces), creating a net vertical etch because the passivation protects sidewalls while the bottom is preferentially etched.
• Scalloping: The alternating etch/passivation cycles create characteristic ripples (scallops) on the sidewall with amplitude of 50-200 nm — these scallops are a reliability concern because they create stress concentration points in the subsequent liner and barrier layers.
• Etch Rate: Typical DRIE etch rates for TSV are 5-20 μm/min depending on via diameter and aspect ratio — a 100 μm deep TSV takes 5-20 minutes to etch.

Why DRIE Matters for TSV

• Geometry Control: The TSV diameter, depth, and sidewall profile directly determine the via's electrical resistance, capacitance, mechanical stress, and fill quality — DRIE must achieve tight control over all these parameters across thousands of vias per die.
• Aspect Ratio Capability: Production TSVs require aspect ratios of 5:1 to 10:1 (5-10 μm diameter × 50-100 μm depth) — DRIE is the only etching technology capable of achieving these geometries in silicon with acceptable throughput.
• Sidewall Quality: The liner, barrier, and seed layers deposited after etching must conformally coat the via sidewalls — rough or re-entrant sidewall profiles cause coverage gaps that lead to barrier failure and copper diffusion into silicon.
• Throughput: DRIE etch time is a significant contributor to TSV fabrication cost — faster etch rates with maintained profile quality directly reduce manufacturing cost per wafer.

DRIE Process Parameters

• Etch Gas: SF₆ at 100-500 sccm — provides fluorine radicals that react with silicon to form volatile SiF₄.
• Passivation Gas: C₄F₈ at 50-200 sccm — deposits a thin (~50 nm) fluorocarbon polymer that protects sidewalls from lateral etching.
• Cycle Time: Etch 1-5 seconds, passivation 1-3 seconds — shorter cycles reduce scallop amplitude but decrease net etch rate.
• RF Power: 1-3 kW source power (plasma generation) + 10-50 W bias power (ion directionality) — higher bias improves anisotropy but increases sidewall damage.
• Temperature: Wafer chuck at -10 to 20°C — lower temperature improves passivation adhesion and etch selectivity.
• Pressure: 10-50 mTorr — lower pressure increases ion directionality for more vertical profiles.

DRIE is the foundational etching technology for TSV fabrication — using the Bosch process's alternating etch-passivation cycles to carve high-aspect-ratio vertical holes in silicon with the geometry control, sidewall quality, and throughput required for manufacturing the millions of through-silicon vias in every HBM memory stack and 3D integrated circuit.