Depletion Width (W_dep) is the spatial extent of the charge-depleted region surrounding a p-n or Schottky junction where mobile carriers have been swept away leaving only fixed ionized dopants — it determines junction capacitance, breakdown voltage, leakage current, and the electrostatic control a gate exerts over a transistor channel.

What Is Depletion Width?

• Definition: The total width W = W_p + W_n of the region on both sides of a p-n junction where mobile carrier concentration is negligible compared to ionized dopant concentration, bounded by the depletion approximation.
• Charge Neutrality Constraints: The total depletion charge on each side must be equal (qudot N_A W_p = q N_D * W_n), so the depletion extends further into the lighter-doped side — a one-sided junction (N_A >> N_D) has nearly all depletion in the lightly doped n-side.
• Voltage Dependence: W = sqrt(2epsilon(V_bi + V_R) / (q * N_eff)), where V_R is applied reverse bias and N_eff is the effective doping. Reverse bias widens the depletion; forward bias narrows it.
• Temperature Sensitivity: V_bi decreases with temperature (smaller kTln(N_AN_D/ni^2) as ni increases), which slightly reduces depletion width at elevated temperatures, while thermal generation current increases — a competing effect important for leakage analysis.

Why Depletion Width Matters

• Junction Capacitance: The depletion region acts as the dielectric of a parallel-plate capacitor C_j = epsilon*A/W. Since W depends on voltage, C_j is nonlinear — this voltage-variable capacitance (varactor) is exploited in RF tuning circuits, voltage-controlled oscillators, and voltage-controlled phase shifters.
• Breakdown Voltage: Avalanche breakdown in a p-n junction occurs when the peak electric field in the depletion region reaches the critical field (approximately 3x10^5 V/cm for silicon). Since peak field scales inversely with depletion width at a given voltage, lightly doped junctions with wide depletion regions can sustain higher voltages before breakdown.
• MOSFET Gate Control: In a MOSFET, the gate voltage modulates the depletion width under the gate oxide — threshold voltage is reached when the depletion extends to its maximum value W_dmax = sqrt(4epsilonphi_F/q*N_A), defining the onset of strong inversion.
• DRAM Storage Capacitor: Deep-trench and stacked DRAM capacitors rely on precisely controlled depletion widths to achieve the designed capacitance — variation in substrate doping causes depletion width variability that directly impacts array capacitance and retention uniformity.
• Tunnel Junction Design: Reducing depletion width below approximately 10nm through very heavy doping (above 10^18 cm-3 on both sides) enables Zener tunneling — the mechanism exploited in Zener diodes, Esaki diodes, and tunnel junctions for multi-junction solar cells.

How Depletion Width Is Controlled and Used

• Doping Profile Engineering: Modulating doping concentration across the junction controls depletion asymmetry and electric field distribution — graded junctions and hyper-abrupt profiles are designed for specific electrical characteristics.
• C-V Measurement: Capacitance vs. voltage measurements on test diodes provide depletion width as a function of reverse bias via C = epsilon*A/W, enabling doping profile extraction through the Mott-Schottky relationship.
• Process Simulation: TCAD solves the Poisson equation self-consistently with the carrier equations to predict depletion width and field distribution throughout the device structure, enabling design optimization before fabrication.

Depletion Width is the key electrostatic dimension of every semiconductor junction — its voltage dependence underlies junction capacitance, its magnitude determines breakdown voltage and MOSFET threshold, and its controllability through doping profile engineering provides the primary handle for optimizing diodes, transistors, varactors, and photodetectors across every semiconductor technology platform.