Design for Test (DFT) is the set of design techniques inserted into a chip to make it testable after fabrication — including scan chains, memory BIST, test compression, and boundary scan — that enable Automatic Test Pattern Generation (ATPG) tools to achieve >98% fault coverage and identify manufacturing defects that would otherwise escape to the customer as field failures.
Why DFT Is Essential
A chip with 10 billion transistors cannot be fully tested through its functional I/O pins alone — the internal state space is too large. DFT structures provide controllability (ability to set internal nodes to desired values) and observability (ability to read internal node values from external pins), transforming an opaque black box into a transparent, testable structure.
Core DFT Techniques
- Scan Chain Insertion: Every flip-flop is replaced with a scan flip-flop that has a multiplexed input — normal functional input during operation, and a serial scan input during test mode. All scan flops are stitched into chains that allow shifting test patterns in and capturing results out through dedicated scan I/O pins. A 100M-gate design may have 2000-5000 scan chains operating in parallel.
- Test Compression (CODEC): Raw scan chain data for a large design can be terabytes. Compression logic (Synopsys DFTMAX, Cadence Modus) at the scan input/output reduces data volume by 10-100x. A decompressor fans out compressed patterns from a few scan-in pins to thousands of internal chains; a compactor compresses thousands of chain outputs into a few scan-out pins.
- Memory BIST (Built-In Self-Test): Embedded SRAM arrays (caches, buffers, register files) are tested by on-chip BIST controllers that generate algorithmic patterns (March C-, Checkerboard) and compare results internally. This avoids routing all memory address/data bits to external pins and enables at-speed testing impossible through scan.
- JTAG / Boundary Scan (IEEE 1149.1): A standard 4-wire interface (TDI, TDO, TMS, TCK) enables board-level interconnect testing and on-chip debug. Boundary scan cells at every I/O pad can drive and observe pin states during board test.
- Logic BIST (LBIST): On-chip PRBS (pseudo-random bit sequence) generators create test patterns and MISR (Multiple Input Signature Register) compacts the responses into a signature, enabling field testing without external test equipment.
ATPG and Fault Coverage
- Stuck-At Faults: Model a node permanently at 0 or 1. ATPG generates patterns to detect each possible stuck-at fault. Target: >99% coverage.
- Transition Faults: Model a node that is slow to transition. Tested with at-speed patterns (launch-on-shift or launch-on-capture). Target: >97% coverage.
- IDDQ Testing: Measure quiescent supply current — elevated IDDQ indicates bridging shorts or gate oxide leakage not caught by logic tests.
Design for Test is the engineering investment that makes manufacturing quality measurable — adding 5-10% area overhead to ensure that every defective die is caught at the factory rather than discovered by the customer in the field.