Design Rule Check (DRC) — automated verification that a chip's physical layout complies with all manufacturing rules specified by the foundry.
Types of Rules
- Minimum Width: Wires/features can't be narrower than X nm
- Minimum Spacing: Features must be at least X nm apart
- Enclosure: One layer must extend beyond another by X nm (e.g., metal enclosing via)
- Density: Metal/poly density must be within min/max range for CMP uniformity
- Antenna: Charge accumulation during plasma etch can't exceed limits (protects gate oxide)
Rule Count
- 180nm node: ~500 rules
- 7nm node: ~5,000+ rules
- 3nm node: ~10,000+ rules
- Rules increase exponentially with each node
DRC Flow
1. Extract layout geometry
2. Check every feature against every applicable rule
3. Generate error markers on the layout
4. Engineer fixes violations iteratively
Tools: Synopsys IC Validator, Cadence Pegasus, Siemens Calibre
DRC must be 100% clean before tapeout — a single violation can cause manufacturing failure. There is no tolerance for DRC errors in production masks.