Design Rule Check verifies that a chip layout meets all geometric manufacturing constraints defined by the foundry. Every mask layer must pass DRC before tape-out—violations would cause manufacturing defects or yield loss.

What DRC Checks

Minimum width: Metal lines, poly gates, and other features must be wider than the process minimum. Minimum space: Gap between adjacent features must meet minimum spacing rules. Enclosure: One layer must overlap another by a minimum amount (e.g., contact must be enclosed by metal on all sides). Extension: A layer must extend beyond another by a specified distance. Density: Metal density per unit area must fall within min/max limits (for CMP uniformity). Antenna: Charge accumulation ratios during plasma etch must not exceed limits that damage gate oxide.

DRC Rule Decks

Provided by the foundry for each technology node. Contain thousands to tens of thousands of rules at advanced nodes. Rules are expressed in tool-specific languages (SVRF for Calibre, ICV-R for ICV).

DRC Tools

• Siemens Calibre DRC: Industry gold standard for physical verification • Synopsys IC Validator (ICV): Integrated with Synopsys P&R flow • Cadence Pegasus: Integrated with Cadence P&R flow

DRC Flow

Step 1: Run DRC on full-chip layout → generates error database. Step 2: Review violations in layout editor (highlighted with error markers). Step 3: Fix violations (move shapes, resize features, add fill). Step 4: Re-run DRC. Iterate until clean (0 violations). Clean DRC is required for tape-out signoff.