Device Layer is the thin top silicon film in an SOI wafer — the single-crystal silicon layer where all active transistors (MOSFETs, diodes) are fabricated, sitting atop the buried oxide (BOX) insulator.

What Is the Device Layer?

• Thickness:
• PD-SOI: 50-100 nm (older technology).
• FD-SOI: 5-12 nm (modern, fully depleted channel).
• Thick SOI: 1-100 $mu m$ (MEMS, photonics, power devices).
• Quality: Must be defect-free single-crystal silicon (same quality as bulk prime wafers).
• Uniformity: Thickness uniformity < ±0.5 nm across the wafer (for FD-SOI, thickness directly affects $V_t$).

Why It Matters

• $V_t$ Control: In FD-SOI, the threshold voltage is directly proportional to device layer thickness. ±1 nm = significant $V_t$ shift.
• Performance: Thinner device layers enable better electrostatic control (less short-channel effects).
• Cost Driver: The device layer quality is the primary cost factor of SOI wafers.

Device Layer is the silicon canvas for transistors — the ultra-thin, ultra-pure crystal film where the entire integrated circuit is painted.