<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Threshold voltage: the point a transistor switches, and what blurs it</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Subthreshold slope, DIBL and V&#8202;<tspan font-size="9">th</tspan> roll-off set the leakage-vs-speed tradeoff at every node</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Turning off</text><text x="32" y="106" fill="#8b949e" font-size="10.5">log I<tspan font-size="7" dy="2">D</tspan><tspan dy="-2"> vs gate voltage V</tspan><tspan font-size="7" dy="2">GS</tspan></text><!-- axes --><line x1="52" y1="126" x2="52" y2="300" stroke="#8b949e" stroke-width="1.2"/><line x1="52" y1="300" x2="228" y2="300" stroke="#8b949e" stroke-width="1.2"/><text x="46" y="132" fill="#8b949e" font-size="8" text-anchor="end">log I<tspan font-size="6" dy="2">D</tspan></text><text x="226" y="316" fill="#8b949e" font-size="8" text-anchor="end">V<tspan font-size="6" dy="2">GS</tspan></text><!-- transfer curve: leakage floor -> subthreshold slope -> on --><path d="M60 288 L96 285 L150 168 L200 138 L222 134" fill="none" stroke="#34d399" stroke-width="2"/><!-- Vth marker --><line x1="150" y1="126" x2="150" y2="300" stroke="#a99cf0" stroke-width="1" stroke-dasharray="3 3"/><text x="150" y="122" fill="#a99cf0" font-size="9" text-anchor="middle">V<tspan font-size="6.5" dy="2">th</tspan></text><!-- SS slope annotation --><line x1="104" y1="272" x2="140" y2="188" stroke="#e0b13a" stroke-width="1" stroke-dasharray="2 2"/><text x="158" y="236" fill="#e0b13a" font-size="8.5">slope = SS</text><text x="158" y="248" fill="#e0b13a" font-size="8.5">mV / decade</text><!-- Ioff / Ion --><text x="60" y="283" fill="#f87171" font-size="8">I<tspan font-size="6" dy="2">off</tspan><tspan dy="-2"> (leakage)</tspan></text><circle cx="222" cy="134" r="2.3" fill="#38bdf8"/><text x="218" y="130" fill="#9fd8ef" font-size="8" text-anchor="end">I<tspan font-size="6" dy="2">on</tspan></text><text x="32" y="326" fill="#adb5bd" font-size="9.5">Below V<tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2"> the current doesn't stop &#8212;</tspan></text><text x="32" y="341" fill="#adb5bd" font-size="9.5">it falls exponentially. A steeper</text><text x="32" y="356" fill="#adb5bd" font-size="9.5">slope means a cleaner off-state.</text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#e0b13a" font-size="13" font-weight="700">2 &#183; Short channels lose control</text><text x="279" y="106" fill="#8b949e" font-size="10.5">the drain field lowers the barrier</text><!-- long channel barrier --><text x="290" y="128" fill="#7ee6c0" font-size="9">long channel</text><path d="M285 190 L305 190 Q325 190 328 150 L352 150 Q355 190 375 190 L395 190" fill="none" stroke="#34d399" stroke-width="1.8"/><text x="283" y="200" fill="#8b949e" font-size="7.5">S</text><text x="393" y="200" fill="#8b949e" font-size="7.5">D</text><text x="340" y="145" fill="#7ee6c0" font-size="7.5" text-anchor="middle">high barrier</text><!-- short channel barrier lowered --><text x="290" y="224" fill="#f87171" font-size="9">short channel + high V<tspan font-size="6.5" dy="2">DS</tspan></text><path d="M285 286 L307 286 Q329 286 333 262 L349 258 Q357 280 379 286 L397 286" fill="none" stroke="#f87171" stroke-width="1.8"/><line x1="349" y1="234" x2="349" y2="256" stroke="#f87171" stroke-width="1" marker-end="url(#dn)"/><text x="360" y="246" fill="#f87171" font-size="7.5">barrier pulled down</text><text x="283" y="296" fill="#8b949e" font-size="7.5">S</text><text x="395" y="296" fill="#8b949e" font-size="7.5">D</text><text x="279" y="322" fill="#adb5bd" font-size="9.5">When source and drain get close, the</text><text x="279" y="337" fill="#adb5bd" font-size="9.5">drain steals control from the gate:</text><text x="279" y="352" fill="#adb5bd" font-size="9.5">V<tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2"> drops and leakage climbs.</tspan></text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#9fd8ef" font-size="13" font-weight="700">3 &#183; The 60 mV floor &amp; the fixes</text><text x="526" y="106" fill="#8b949e" font-size="10.5">why SS can't scale, and what does</text><rect x="526" y="118" width="202" height="52" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="136" fill="#f0d9b5" font-size="10" font-weight="700">Boltzmann limit</text><text x="536" y="152" fill="#adb5bd" font-size="9.5">SS &#8805; 60 mV/decade at 300K &#8212; a</text><text x="536" y="165" fill="#adb5bd" font-size="9.5">physics floor from kT/q &#215; ln10.</text><text x="526" y="190" fill="#adb5bd" font-size="9.5">Regain gate control by:</text><circle cx="532" cy="206" r="2" fill="#34d399"/><text x="542" y="209" fill="#adb5bd" font-size="9.5">thinning the body (FD-SOI)</text><circle cx="532" cy="224" r="2" fill="#34d399"/><text x="542" y="227" fill="#adb5bd" font-size="9.5">wrapping the gate (FinFET, GAA)</text><circle cx="532" cy="242" r="2" fill="#34d399"/><text x="542" y="245" fill="#adb5bd" font-size="9.5">halo / pocket implants near S/D</text><circle cx="532" cy="260" r="2" fill="#34d399"/><text x="542" y="263" fill="#adb5bd" font-size="9.5">higher V<tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2"> cells where leakage matters</tspan></text><text x="526" y="290" fill="#8b949e" font-size="9.5">Every node balances a low V<tspan font-size="6.5" dy="2">th</tspan></text><text x="526" y="305" fill="#8b949e" font-size="9.5">(fast, leaky) against a high V<tspan font-size="6.5" dy="2">th</tspan></text><text x="526" y="320" fill="#8b949e" font-size="9.5">(slow, low-power) &#8212; multi-V<tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2"> libraries</tspan></text><text x="526" y="335" fill="#8b949e" font-size="9.5">let designers pick per path.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Subthreshold slope (SS)</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">mV of V<tspan font-size="6.5" dy="2">GS</tspan><tspan dy="-2"> to cut current 10&#215;.</tspan></text><text x="32" y="440" fill="#adb5bd" font-size="9.5">Lower = a sharper off-switch.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#f87171" font-size="11" font-weight="700">DIBL</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">Drain-induced barrier lowering:</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">V<tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2"> sags as V</tspan><tspan font-size="6.5" dy="2">DS</tspan><tspan dy="-2"> rises.</tspan></text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#e0b13a" font-size="11" font-weight="700">V<tspan font-size="7" dy="2">th</tspan><tspan dy="-2"> roll-off</tspan></text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Threshold falls as gate length</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">shrinks &#8212; a short-channel effect.</text><defs><marker id="dn" markerWidth="6" markerHeight="6" refX="3" refY="5" orient="auto"><path d="M0 0 L6 0 L3 6 z" fill="#f87171"/></marker></defs></svg>

Drain-Induced Barrier Lowering (DIBL) is the short-channel effect where the drain voltage reduces the source-channel potential barrier, causing the threshold voltage to decrease with increasing drain bias — quantified in mV/V and serving as a primary metric for electrostatic integrity of the transistor channel, with DIBL directly determining the distinction between "on" and "off" states in scaled transistors.

Physical Mechanism: In a long-channel MOSFET, the potential barrier between source and channel is controlled solely by the gate voltage. In a short-channel device, the drain depletion region extends close enough to the source that the drain voltage also influences the barrier height. Higher V_DS lowers the source-channel barrier, allowing more carriers to flow even below the nominal threshold voltage.

DIBL Quantification: DIBL = -(V_th,low_VDS - V_th,high_VDS) / (V_DS,high - V_DS,low) in mV/V. For example, if V_th at V_DS = 0.05V is 300mV and V_th at V_DS = 0.75V is 270mV: DIBL = -(300 - 270) / (0.75 - 0.05) = 43 mV/V.

DIBL Targets by Generation:

Impact on Circuit Design: DIBL causes the transistor I_off to increase when the drain is at V_DD (which is the normal operating condition for the "off" transistor in CMOS logic). This means static leakage power is higher than V_th measurements at low V_DS would suggest. For SRAM, DIBL degrades the static noise margin because the access transistor's effective V_th drops under the bit-line voltage, weakening the stored data.

DIBL Mitigation Approaches:

DIBL vs. Other Short-Channel Effects: DIBL is closely related to but distinct from: V_th roll-off (V_th decreases with shorter gate length even at low V_DS, due to charge sharing); punchthrough (the extreme case where S/D depletion regions merge and gate loses control entirely); and subthreshold slope degradation (the on/off transition becomes less steep as DIBL increases, approaching the 60mV/dec thermal limit from above).

DIBL serves as the essential figure of merit for transistor electrostatic integrity — a single number that captures how effectively the gate controls the channel against drain interference, and whose progressive reduction from >100 mV/V in planar to <15 mV/V in GAA architectures traces the history of transistor scaling innovation.