Multi-Die Chiplet Design is the architectural approach of decomposing a monolithic chip into multiple smaller dies (chiplets) that are co-packaged and interconnected — enabling mix-and-match of different process nodes, higher aggregate transistor count, improved yield (smaller dies yield better), and faster time-to-market through die reuse, fundamentally changing how high-performance chips are designed and manufactured.
Why Chiplets?
| Aspect | Monolithic | Chiplet |
|---|---|---|
| Die size limit | Reticle limit (~850 mm²) | No limit (package multiple dies) |
| Yield | Large die = low yield | Small dies = high yield |
| Process node | All logic on same node | Each chiplet on optimal node |
| Time to market | Full chip redesign | Swap/upgrade individual chiplets |
| Cost | $$$ (large die) | $$ (smaller dies, better yield) |
Die-to-Die (D2D) Interconnect Standards
| Interface | Bandwidth | Reach | Bump Pitch | Power |
|---|---|---|---|---|
| UCIe 1.0 | 32 GT/s/lane | < 2 mm (standard) | 25-55 μm | 0.5 pJ/bit |
| BoW (Bunch of Wires) | Custom | < 10 mm | 45-55 μm | 0.5-1 pJ/bit |
| AIB (Intel) | 2 Gbps/bump | < 2 mm | 55 μm | 0.85 pJ/bit |
| Infinity Fabric (AMD) | ~AMD proprietary | < 50 mm | Standard C4 | ~2 pJ/bit |
| LIPINCON (TSMC) | 5.4 Gbps/bump | < 1 mm | 25 μm | 0.38 pJ/bit |
UCIe (Universal Chiplet Interconnect Express)
- Industry standard (Intel, AMD, ARM, TSMC, Samsung).
- Two variants: Standard package (C4 bumps) and advanced package (microbumps).
- Protocol layers: Raw D2D PHY → adaptor → CXL/PCIe/custom protocol.
- Goal: Chiplets from different vendors interoperate in the same package.
Chiplet Integration Technologies
- 2.5D (Silicon Interposer): Chiplets on Si interposer with TSVs — TSMC CoWoS, Intel EMIB.
- 3D Stacking: Chiplets stacked vertically — hybrid bonding (< 1 μm pitch).
- Fan-Out (FOWLP): Chiplets embedded in mold compound with RDL — TSMC InFO.
- Bridge: Embedded Si bridge connects adjacent chiplets — Intel EMIB (short-reach, high-density).
Design Challenges
- Thermal: Multiple active dies in close proximity — thermal coupling and hotspots.
- Power delivery: Shared PDN must supply all chiplets — complex IR drop analysis.
- Testing: Each chiplet tested independently (Known Good Die) before assembly.
- Design partitioning: Where to split the design across chiplets — minimize D2D bandwidth.
- Latency: D2D interconnect adds 1-5 ns per crossing — impacts cache coherency.
Industry Examples
- AMD EPYC (Zen): Up to 12 CCD (Core Complex Die) chiplets + 1 IOD.
- Intel Ponte Vecchio: 47 tiles (chiplets) across 5 process nodes.
- Apple M1 Ultra: Two M1 Max dies connected via UltraFusion (2.5 TB/s).
- AMD MI300X: 8 XCD + 4 IOD on 3D stacked HBM — largest GPU package.
Multi-die chiplet design is the dominant architecture for next-generation high-performance computing — by breaking the monolithic die size and yield constraints, chiplets enable the construction of systems with more transistors, better economics, and faster innovation cycles than any monolithic approach can deliver.
Related Topics
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.