Die-to-Die (D2D) Interconnect is the high-bandwidth, low-latency communication link between chiplets within a multi-die package — providing the electrical connections that make separately fabricated dies function as a unified chip, with performance metrics (bandwidth density in Gbps/mm, energy efficiency in pJ/bit, latency in nanoseconds) that must approach on-chip wire performance to avoid becoming a system bottleneck.

What Is Die-to-Die Interconnect?

• Definition: The physical and protocol layers that enable data transfer between two or more dies within the same package — encompassing the bump/bond interconnects, PHY (physical layer) circuits, and protocol logic that together determine the bandwidth, latency, and energy cost of inter-chiplet communication.
• Performance Requirements: D2D interconnects must achieve bandwidth density > 100 Gbps/mm of die edge, energy < 0.5 pJ/bit, and latency < 2 ns to avoid becoming a performance bottleneck — these targets are 10-100× more demanding than chip-to-chip links over a PCB.
• Parallel Architecture: Unlike long-distance SerDes links that use few high-speed lanes (56-112 Gbps each), D2D interconnects use many parallel lanes at moderate speed (2-16 Gbps each) — the short distance (< 10 mm) allows parallel signaling without the power cost of serialization.
• Bump-Limited: D2D bandwidth is ultimately limited by the number of bumps/bonds at the die edge — finer pitch interconnects (micro-bumps → hybrid bonding) directly increase available bandwidth.

Why D2D Interconnect Matters

• Chiplet Viability: The entire chiplet architecture depends on D2D interconnects being fast and efficient enough that splitting a monolithic die into chiplets doesn't create a performance penalty — if D2D is too slow or power-hungry, chiplets lose their advantage.
• Memory Bandwidth: HBM connects to the GPU through D2D links on the interposer — the 1024-bit wide HBM interface at 3.2-9.6 Gbps per pin delivers 460 GB/s to 1.2 TB/s per stack through D2D interconnects.
• Compute Scaling: Multi-chiplet processors (AMD EPYC, Intel Xeon) need D2D bandwidth that scales with core count — insufficient D2D bandwidth creates a "chiplet wall" where adding more compute chiplets doesn't improve system performance.
• Heterogeneous Integration: D2D interconnects must support diverse traffic patterns — cache coherency between CPU chiplets, memory requests to HBM, I/O traffic to SerDes chiplets — each with different bandwidth and latency requirements.

D2D Interconnect Technologies

• AMD Infinity Fabric: AMD's proprietary D2D interconnect for Ryzen/EPYC — 32 bytes/cycle at up to 2 GHz, providing ~36 GB/s per link between CCDs and IOD.
• Intel EMIB: Embedded Multi-Die Interconnect Bridge — silicon bridge in organic substrate providing ~100 Gbps/mm bandwidth density between adjacent tiles.
• TSMC LSI/CoWoS: Silicon interposer-based D2D with fine-pitch routing — supports > 1 TB/s aggregate bandwidth between chiplets on CoWoS-S.
• UCIe (Universal Chiplet Interconnect Express): Open standard D2D interface — UCIe 1.0 specifies 28 Gbps/lane with 1317 Gbps/mm bandwidth density on advanced packaging.
• BoW (Bunch of Wires): OCP-backed open D2D standard — simple parallel interface optimized for short-reach, low-power chiplet communication.

Die-to-die interconnect is the critical enabling technology for chiplet architectures — providing the high-bandwidth, low-latency, energy-efficient communication links that make multi-die packages function as unified chips, with interconnect performance directly determining whether chiplet-based designs can match or exceed the performance of monolithic alternatives.