Die to die interconnect definition and engineering boundary. is the short-reach electrical and protocol connection between chiplets inside one package. It can deliver far greater bandwidth density and lower energy per bit than board links because reach is millimeters and pins are dense. Implementations use organic redistribution, micro-bumps on interposers, silicon bridges, and increasingly fine-pitch hybrid bonding; a protocol such as UCIe may run above the physical connection. Bandwidth claims from one to many terabytes per second are package- and design-specific, not an intrinsic property of every D2D link. Evaluate bidirectional delivered bandwidth, edge or area density, pJ per bit, latency, BER, lane repair, clocking, protocol overhead, reach, bump pitch, routing layers, escape, yield, and test. Micro-bumps may be tens of micrometers; advanced hybrid bonding can reach much finer pitch, but exact production capability depends on foundry, assembly flow, alignment, surface preparation, and die size. A useful specification begins with workloads and service objectives rather than peak arithmetic. It records tensor shapes, sparsity, precision and accumulator behavior; model size and reuse; batch and sequence distributions; latency percentiles; required throughput; memory capacity and bandwidth; host traffic; collective communication; power, thermal and area limits; availability; security; software versions; and cost. Every published number needs its operating point, data type, workload, compiler, clock, utilization method, and whether it is measured or theoretical. Without that context, TOPS, FLOPS, bandwidth, and energy figures are not comparable.
Architecture, execution, and data movement. Transmitter and receiver PHYs initialize, train clocks and lanes, deskew, detect and repair faults, carry flow-controlled traffic, monitor errors, and coordinate resets and power. The protocol above may be coherent, packetized, streaming, or memory-specific. Modern acceleration is a hierarchy: host processors orchestrate work, a runtime and compiler lower graphs into kernels, DMA engines move tensors, local SRAM captures reuse, arithmetic arrays execute dense or sparse operations, vector and scalar units handle nonlinear and control work, and external memory holds parameters and activations that do not fit on chip. Networks, package links, and coherency connect devices. The design is balanced only when compute, storage, movement, synchronization, and software can sustain one another under the target workload. Compilation is part of the architecture. Graph capture, operator legalization, fusion, layout selection, tiling, partitioning, scheduling, precision conversion, buffer allocation, collective insertion, code generation, and runtime dispatch determine whether the hardware is occupied. Dynamic shapes, small batches, irregular sparsity, unsupported operators, and host-device boundaries create bubbles or fallback. A healthy platform exposes counters and deterministic intermediate representations so teams can explain a result instead of tuning an opaque benchmark.
Implementation and physical realization. Co-design PHY, bumps, RDL/interposer/bridge, ESD strategy, clocking, power delivery, return paths, thermal stack, mechanical stress, DFT, known-good die, repair, firmware and protocol. Edge placement and shoreline compete with power bumps and package escape. Implementation proceeds from trace-driven models and roofline analysis through microarchitecture, RTL, verification, physical design, packaging, firmware, compiler, runtime, framework integration, and fleet qualification. Designers budget cycles and bytes for every stage, size queues against burstiness, partition clock and voltage domains, place memories close to consumers, pipeline long wires, protect CDC and reset crossings, add DFT and telemetry, and reserve margin for process, voltage, temperature, aging, and workload drift. Power intent, thermal maps, package escape, signal integrity, and memory availability are architectural inputs, not late signoff details. Specialization removes instruction overhead and unnecessary data motion, but it narrows the efficient workload envelope. Larger arrays raise peak throughput yet waste lanes on unfavorable dimensions. More SRAM improves reuse but consumes die area and leakage. Narrow precision saves bandwidth and energy but demands calibration and numerically sound accumulation. Sparse execution helps only when metadata, load balance, and software preserve useful sparsity. Chiplets improve yield and reuse while adding link energy, latency, test, thermal, and package dependencies. The correct design optimizes delivered application value rather than one isolated component.
Verification, security, and production operation. Use extracted channel and package models, jitter and eye analysis, crosstalk, BER, training, repair, protocol stress, voltage and temperature corners, power noise, mechanical reliability, bonding void inspection, package test, and system fault injection. Verification combines reference-model comparison, arithmetic corner cases, protocol assertions, formal checks, constrained-random traffic, coherency and memory-order tests, CDC/RDC, power-state verification, emulation, compiler differential testing, operator and model suites, fault injection, post-layout timing and power analysis, silicon characterization, and long-running system stress. Accuracy is checked end to end after quantization and graph transformations. Performance testing reports warmup, steady state, percentiles, utilization, throttling, error bars, and reproducible software. Recovery tests cover malformed commands, link errors, memory faults, reset during work, and partial device failure. The trust boundary includes boot ROM, fuses, device firmware, management controllers, debug, DMA, shared memory, package links, compiler artifacts, model weights, and telemetry. Secure and measured boot, authenticated firmware, anti-rollback, IOMMU isolation, memory protection, zeroization, debug authorization, side-channel review, supply-chain provenance, and incident response are designed together. Multi-tenant accelerators also require scheduling and state-clearing rules that prevent one workload from observing another. Production operation needs admission control, isolation, scheduling, observability, firmware and compiler compatibility, signed updates, rollback, health checks, thermal and power management, error containment, and capacity models. Counters should attribute stalls to compute, memory, fabric, synchronization, compilation, or host overhead. Fleet telemetry closes the loop with architecture and software teams, but collection must respect tenant boundaries and data governance. Service owners define degraded modes and replacement policy before hardware faults appear.
| Physical option | Pitch class | Routing density | Strength | Primary challenge |
|---|---|---|---|---|
| Organic RDL/substrate | Coarser | Moderate | Cost and broad assembly | Energy and shoreline |
| Micro-bump interposer | Fine | High | Mature 2.5D bandwidth | Interposer and bump yield |
| Silicon bridge | Fine local | High at die edges | Dense local connection | Placement and bridge process |
| Fan-out RDL | Fine package redistribution | High without full interposer | Thin heterogeneous package | Warpage and RDL yield |
| Hybrid bonding | Very fine, potentially sub-10 µm | Very high | Low parasitic and 3D density | Surface, alignment, test, repair |
<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">UCIe: an open, PCIe-like standard for die-to-die links</text><text x="20" y="50" fill="#8b949e" font-size="12.5">A layered stack over standard or advanced packages lets chiplets from any vendor or node snap together in one package</text><!-- ===== PANEL 1: layered like PCIe ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#38bdf8" font-size="12" font-weight="700">1 · Layered like PCIe</text><rect x="32" y="120" width="40" height="76" fill="#38506a" stroke="#6f8fb0"/><text x="52" y="161" fill="#dbe7f3" font-size="8.5" text-anchor="middle" transform="rotate(-90 52 161)">Die A</text><rect x="194" y="120" width="40" height="76" fill="#6b5fb0" stroke="#8f83c9"/><text x="214" y="161" fill="#e9e3ff" font-size="8.5" text-anchor="middle" transform="rotate(-90 214 161)">Die B</text><rect x="78" y="120" width="110" height="23" fill="#122b22" stroke="#3f9d6f"/><text x="133" y="131" fill="#7ee6c0" font-size="8" text-anchor="middle" font-weight="700">Protocol layer</text><text x="133" y="140" fill="#adb5bd" font-size="6.8" text-anchor="middle">PCIe / CXL / raw streaming</text><rect x="78" y="144" width="110" height="23" fill="#2e2617" stroke="#e0b13a"/><text x="133" y="155" fill="#e0b13a" font-size="8" text-anchor="middle" font-weight="700">Die-to-die adapter</text><text x="133" y="164" fill="#adb5bd" font-size="6.8" text-anchor="middle">link state · CRC · retry · arbitration</text><rect x="78" y="168" width="110" height="23" fill="#10263a" stroke="#38bdf8"/><text x="133" y="179" fill="#38bdf8" font-size="8" text-anchor="middle" font-weight="700">Physical layer</text><text x="133" y="188" fill="#adb5bd" font-size="6.8" text-anchor="middle">bumps · lanes · clock · sideband</text><g fill="#e0b13a"><circle cx="88" cy="197" r="2"/><circle cx="100" cy="197" r="2"/><circle cx="112" cy="197" r="2"/><circle cx="124" cy="197" r="2"/><circle cx="136" cy="197" r="2"/><circle cx="148" cy="197" r="2"/><circle cx="160" cy="197" r="2"/><circle cx="172" cy="197" r="2"/></g><text x="32" y="222" fill="#adb5bd" font-size="8.6">UCIe stacks like PCIe: a physical layer,</text><text x="32" y="234" fill="#adb5bd" font-size="8.6">a die-to-die adapter, and a protocol layer</text><text x="32" y="246" fill="#adb5bd" font-size="8.6">that just carries PCIe, CXL, or raw streams.</text><text x="32" y="268" fill="#38bdf8" font-size="8.6" font-weight="600">Existing software works across the die edge.</text><text x="32" y="290" fill="#8b949e" font-size="8.4">A sideband channel trains and repairs</text><text x="32" y="302" fill="#8b949e" font-size="8.4">lanes; CRC + retry keep the link reliable.</text><text x="32" y="324" fill="#8b949e" font-size="8.4">Buy an I/O die from one vendor, a compute</text><text x="32" y="336" fill="#8b949e" font-size="8.4">die from another — they interoperate.</text><!-- ===== PANEL 2: pick your package ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#a99cf0" font-size="12" font-weight="700">2 · Pick your package</text><text x="380" y="106" fill="#dbe7f3" font-size="8.3" text-anchor="middle" font-weight="700">standard package (organic)</text><rect x="298" y="114" width="42" height="16" fill="#38506a" stroke="#6f8fb0"/><rect x="420" y="114" width="42" height="16" fill="#6b5fb0" stroke="#8f83c9"/><rect x="290" y="132" width="182" height="9" fill="#5a4632" stroke="#6f6f6a"/><g fill="#c98a2e"><circle cx="308" cy="131" r="2.4"/><circle cx="322" cy="131" r="2.4"/><circle cx="334" cy="131" r="2.4"/><circle cx="428" cy="131" r="2.4"/><circle cx="442" cy="131" r="2.4"/><circle cx="454" cy="131" r="2.4"/></g><line x1="342" y1="122" x2="418" y2="122" stroke="#8b949e" stroke-width="0.7" stroke-dasharray="3 2"/><text x="380" y="120" fill="#8b949e" font-size="6.6" text-anchor="middle">reach 10–25 mm</text><text x="380" y="154" fill="#adb5bd" font-size="7.6" text-anchor="middle">coarse pitch · lower density · cheaper</text><text x="380" y="176" fill="#dbe7f3" font-size="8.3" text-anchor="middle" font-weight="700">advanced package (2.5D interposer)</text><rect x="330" y="184" width="44" height="16" fill="#38506a" stroke="#6f8fb0"/><rect x="388" y="184" width="44" height="16" fill="#6b5fb0" stroke="#8f83c9"/><text x="381" y="182" fill="#8b949e" font-size="6.6" text-anchor="middle">~2 mm</text><rect x="312" y="202" width="148" height="9" fill="#2b2f36" stroke="#6f6f6a"/><g fill="#b8732e"><circle cx="338" cy="201" r="1.3"/><circle cx="346" cy="201" r="1.3"/><circle cx="354" cy="201" r="1.3"/><circle cx="362" cy="201" r="1.3"/><circle cx="370" cy="201" r="1.3"/><circle cx="378" cy="201" r="1.3"/><circle cx="386" cy="201" r="1.3"/><circle cx="394" cy="201" r="1.3"/><circle cx="402" cy="201" r="1.3"/><circle cx="410" cy="201" r="1.3"/><circle cx="418" cy="201" r="1.3"/><circle cx="426" cy="201" r="1.3"/></g><text x="380" y="224" fill="#7ee6c0" font-size="7.6" text-anchor="middle">fine pitch · high density · sub-0.5 pJ/bit</text><line x1="279" y1="236" x2="481" y2="236" stroke="#30363d" stroke-width="1"/><text x="279" y="256" fill="#adb5bd" font-size="8.6">The same UCIe stack runs on both. You</text><text x="279" y="268" fill="#adb5bd" font-size="8.6">pick the package for your cost-versus-</text><text x="279" y="280" fill="#adb5bd" font-size="8.6">bandwidth target.</text><text x="279" y="302" fill="#a99cf0" font-size="8.6" font-weight="600">Reach trades against bandwidth density.</text><!-- ===== PANEL 3: what it's really for ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#34d399" font-size="12" font-weight="700">3 · What it's really for</text><text x="526" y="108" fill="#e6edf3" font-size="10" font-weight="700">Figures of merit</text><text x="526" y="126" fill="#adb5bd" font-size="8.7">• bandwidth per mm of die edge</text><text x="526" y="142" fill="#adb5bd" font-size="8.7">• energy per bit (adv: <0.5 pJ/bit)</text><text x="526" y="158" fill="#adb5bd" font-size="8.7">• die-to-die latency < ~2 ns</text><text x="526" y="176" fill="#8b949e" font-size="8">Not raw speed — edge is scarce, so it's</text><text x="526" y="188" fill="#8b949e" font-size="8">bandwidth and energy per bit that count.</text><line x1="526" y1="200" x2="728" y2="200" stroke="#30363d" stroke-width="1"/><text x="526" y="219" fill="#34d399" font-size="10" font-weight="700">Ends the proprietary links</text><text x="526" y="237" fill="#adb5bd" font-size="8.6">Infinity Fabric, EMIB/AIB and NVLink-C2C</text><text x="526" y="249" fill="#adb5bd" font-size="8.6">each stitch one vendor's dies. UCIe is</text><text x="526" y="261" fill="#adb5bd" font-size="8.6">open, so dies from different vendors and</text><text x="526" y="273" fill="#adb5bd" font-size="8.6">process nodes mix in one package.</text><text x="526" y="295" fill="#34d399" font-size="8.6" font-weight="600">→ a marketplace of composable dies.</text><text x="526" y="315" fill="#8b949e" font-size="8.3">Crossing a die edge feels almost on-die.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="404" fill="#38bdf8" font-size="10.5" font-weight="700">Layered like PCIe</text><text x="32" y="421" fill="#adb5bd" font-size="8.7">Physical layer, D2D adapter, protocol</text><text x="32" y="434" fill="#adb5bd" font-size="8.7">layer — and the top reuses PCIe/CXL, so</text><text x="32" y="447" fill="#adb5bd" font-size="8.7">software crosses the die edge unchanged.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="404" fill="#a99cf0" font-size="10.5" font-weight="700">Two package classes</text><text x="279" y="421" fill="#adb5bd" font-size="8.7">Standard organic for reach and low cost;</text><text x="279" y="434" fill="#adb5bd" font-size="8.7">advanced 2.5D for density and pJ/bit —</text><text x="279" y="447" fill="#adb5bd" font-size="8.7">one stack, two cost/bandwidth points.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="404" fill="#34d399" font-size="10.5" font-weight="700">Open beats proprietary</text><text x="526" y="421" fill="#adb5bd" font-size="8.7">One standard link turns chiplets from a</text><text x="526" y="434" fill="#adb5bd" font-size="8.7">one-vendor trick into an ecosystem of</text><text x="526" y="447" fill="#adb5bd" font-size="8.7">mix-and-match, composable dies.</text></svg>
Selection, applications, and lifecycle ownership. Organic links fit cost and coarser density; silicon bridges and interposers fit dense routing; hybrid bonding targets exceptional density and energy at greater process complexity. CPU and GPU tiles, HBM interfaces, cache dies, I/O chiplets, photonic engines, and 3D stacked logic use D2D. Requirements, workloads, datasets, model and compiler versions, architecture models, RTL, IP, timing and power constraints, package and board revisions, firmware, runtime, validation evidence, calibration, test limits, errata, field telemetry, and release approvals remain linked. A hardware generation cannot be patched like an application, so interface compatibility, diagnostic reach, spare capacity, and support lifetime matter. Cross-functional ownership prevents a local optimization from moving cost or risk into memory, packaging, cooling, software, manufacturing, or customer operations. A useful specification begins with workloads and service objectives rather than peak arithmetic. It records tensor shapes, sparsity, precision and accumulator behavior; model size and reuse; batch and sequence distributions; latency percentiles; required throughput; memory capacity and bandwidth; host traffic; collective communication; power, thermal and area limits; availability; security; software versions; and cost. Every published number needs its operating point, data type, workload, compiler, clock, utilization method, and whether it is measured or theoretical. Without that context, TOPS, FLOPS, bandwidth, and energy figures are not comparable. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.
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