All-Digital PLL (ADPLL) is the phase-locked loop implementation where all signal processing is performed in the digital domain — replacing the analog charge pump, loop filter, and VCO with digital equivalents (time-to-digital converter, digital loop filter, and digitally-controlled oscillator) — enabling integration in standard digital CMOS processes without specialty analog devices, easy portability across process nodes, straightforward digital test and calibration, and superior immunity to analog noise coupling from digital switching. ADPLLs are now used in mobile SoCs, IoT devices, and even some high-speed SerDes applications.

ADPLL vs. Analog PLL Comparison

ADPLL Block Diagram

Ref CLK → [TDC] → [Digital Loop Filter] → [DCO] → Output CLK
              ↑                                          |
              └──────── [÷N Divider] ←──────────────────┘

TDC (Time-to-Digital Converter)

• Measures phase error between reference clock and feedback clock in digital units (time → number).
• Resolution: 1 inverter delay (~10–30 ps at 7nm) → quantization noise floor.
• Types:
• Vernier TDC: Two chains of inverters with slightly different delays → differential measurement → fine resolution.
• Flash TDC: Parallel delay chain tap comparators → measure phase in one cycle.
• TDC noise is the dominant phase noise source in ADPLL at high offset frequencies.

DCO (Digitally-Controlled Oscillator)

• LC oscillator with digitally switched capacitor array → tune frequency by switching capacitor banks.
• Coarse bank: Large capacitors (50–200 aF each) → wide tuning range (±10–20%).
• Fine bank: Small capacitors (1–5 aF each) → fine frequency resolution.
• Dithering (ΣΔ modulation): Toggle fine bank bits with ΣΔ → achieve sub-LSB average frequency → fractional-N operation.
• Ring oscillator DCO: Also used (cheaper, smaller, but worse phase noise).

Fractional-N ADPLL

• Divide ratio N can be non-integer (e.g., N=38.5) using ΣΔ modulation of divider.
• ΣΔ alternates between N=38 and N=39 to achieve average N=38.5.
• Enables precise sub-ppm frequency synthesis → needed for wireless standards (LTE, Wi-Fi channel spacing).
• ΣΔ quantization noise shapes → high-frequency noise → filtered by loop bandwidth.

ADPLL Jitter Contributions

• TDC quantization noise: σ_TDC ≈ T_inv / √12 (uniform quantization noise).
• DCO phase noise: Flicker + thermal noise in LC tank → 1/f² behavior.
• Digital loop filter: Must be wide enough to filter TDC noise but narrow enough not to pass DCO noise.
• Total integrated jitter: Typically 0.5–2 ps RMS for ADPLL at mobile frequencies.

Applications of ADPLL

Intel ADPLL Heritage

• MediaTek was a pioneer in commercial ADPLL-based mobile transceivers (2000s).
• Texas Instruments (TI) developed ADPLL theory (Robert Staszewski) for DRP (Digital Radio Processor).
• Apple M-series, Qualcomm Snapdragon: ADPLL in PLL subsystems for portability across TSMC nodes.

The all-digital PLL is the clock synthesis solution that made CMOS process portability a reality — by replacing sensitive analog RC filters and VCOs with digital equivalents that scale automatically with each new process node, ADPLLs enable chip designers to port an entire transceiver or clock generation subsystem to a new foundry or process with minimal re-design effort, dramatically reducing the time-to-market for mobile and IoT SoCs.