Digital-to-Analog Converter (DAC) Design is the mixed-signal circuit discipline that converts digital codes into precise analog voltages or currents — enabling signal generation for communications transmitters, display drivers, audio reproduction, and arbitrary waveform generation, where the DAC's linearity (SFDR), speed (update rate), resolution (bits), and settling time determine the quality of the reconstructed analog signal.

DAC Architectures

Current-Steering DAC:

• An array of weighted current sources, each switched on or off by the corresponding digital bit. Output current is the sum of active sources, converted to voltage by a load resistor or transimpedance amplifier.
• Speed: fastest architecture (up to 100+ GS/s). Resolution: 8-16 bits. Used in communications transmitters (5G base stations), radar.
• Key design: binary-weighted (each source is 2× the previous) or thermometer-coded (2^N−1 equal sources for N bits, selected by decoder). Thermometer coding guarantees monotonicity and reduces glitch energy.

Resistor String (R-String) DAC:

• 2^N resistors in series, with switches selecting the appropriate tap. Inherently monotonic. Low power, small area for low resolution.
• Speed: limited by switch resistance × capacitance. Resolution: 8-12 bits. Used in sensor trimming, bias generation, display drivers.

R-2R Ladder DAC:

• Network of resistors with only two values (R and 2R), creating binary-weighted voltage division. Compact — only 2N resistors for N bits.
• Speed: moderate. Resolution: 8-16 bits. Used in precision instrumentation, audio.

Segmented DAC (Hybrid):

• Combines thermometer-coded MSBs (for linearity) with binary-weighted LSBs (for area efficiency). Example: 16-bit DAC with 6-bit thermometer (63 unit sources) + 10-bit binary.
• The standard architecture for high-performance DACs, balancing linearity, area, and power.

Linearity Metrics

• DNL (Differential Non-Linearity): Deviation of each code step from the ideal 1 LSB. DNL > 1 LSB causes non-monotonicity (output decreases when code increases) — catastrophic for feedback systems.
• INL (Integral Non-Linearity): Cumulative deviation from the ideal transfer function. Measured in LSBs.
• SFDR (Spurious-Free Dynamic Range): Ratio of the fundamental output to the largest spurious tone. For communications: SFDR > 70 dBc required. Dominated by current source mismatch and timing skew.

High-Speed DAC Design Challenges

• Current Source Matching: Unit current source mismatch directly limits INL and SFDR. At 14-bit resolution, sources must match to <0.01%. Device sizing (large W×L for mismatch) conflicts with speed (parasitic capacitance). Calibration (background trimming of current sources) extends effective resolution.
• Glitch Energy: When the digital code transitions, intermediate states cause transient output spikes (glitches). Return-to-zero (RZ) or deglitcher circuits suppress glitches but reduce output power.
• Clock Jitter Sensitivity: DAC output noise from clock jitter increases with output frequency. At 5 GHz output, 100 fs jitter degrades SFDR by ~6 dB. Ultra-low-jitter clock distribution essential.
• Output Bandwidth: The DAC output spectrum follows a sinc(πf/fs) envelope — output power rolls off at Nyquist. RF DACs use 2-4× oversampling with digital upconversion to place the signal at higher frequencies.

Digital-to-Analog Converter Design is the complementary half of the analog-digital interface — the circuit that transforms digital computations back into the analog signals that drive antennas, speakers, displays, and actuators in the physical world.