CMP dishing is the undesirable formation of a concave recessed surface profile in metal interconnect lines during chemical mechanical planarization, occurring when the polishing pad elastically flexes into wide metal trenches and removes metal faster than the surrounding harder dielectric field oxide. In copper and tungsten dual-damascene metallization, differences in mechanical hardness, Young's modulus, and chemical oxidation rates between the metal and the adjacent dielectric barrier layer (such as silicon dioxide or SiCN) lead to preferential metal loss once the over-polish phase begins. Dishing reduces the effective cross-sectional area of interconnect wires ($A_{\text{eff}} = w \cdot (t_0 - h_{\text{dish}})$), triggering localized resistance spikes, severe RC interconnect delay variations, and surface topography steps that degrade lithographic depth of focus in subsequent wiring levels.

Elastic pad bending under down-force pressure governs the physics of trench dishing. In chemical mechanical polishing, the polishing pad behaves as an elastic plate supported by rigid dielectric field oxide mesas. When the pad spans an open metal trench of width $w$, the downward pressure ($P_{\text{down}}$) causes the polyurethane pad to flex downward according to classical beam deflection mechanics:

where $E_{\text{pad}}$ is the elastic modulus of the pad, $I_{\text{pad}}$ is the pad area moment of inertia, and $R_{\text{chemical}}$ is the chemical static etch rate of the copper slurry in the absence of mechanical contact. Because pad deflection scales with the fourth power of trench width ($w^4$), narrow lines ($w < 0.2\ \mu\text{m}$) experience negligible dishing ($< 2\text{ nm}$), whereas wide power buses and bond pads ($w > 10\ \mu\text{m}$) suffer extreme dishing exceeding $30\text{--}50\text{ nm}$ if unmitigated.

Over-polish duration and barrier removal chemistry accelerate dishing progression. During dual-damascene CMP, polishing proceeds through three sequential phases: bulk copper removal, barrier (TaN/Ta or Ru/Co) clearing, and oxide over-polish. To ensure complete barrier clearing across wafer-scale non-uniformity without leaving electrical bridging shorts, a $20\text{--}30\%$ over-polish margin is mandatory. During this over-polish phase, abrasive silica or alumina nanoparticles in the slurry continue to abrade the softer copper line at a rate faster than the underlying dielectric field, deepening the dished recess.

Reduced conductor cross-sections from excessive dishing cause severe resistance inflation and timing skew. As dishing thins the metal wire, the cross-sectional area drops from its nominal design ($A_0 = w \cdot t_0$) to $A_{\text{eff}} \approx w \cdot (t_0 - 0.67 h_{\text{dish}})$. This geometry shrinkage increases line resistance proportionally ($R = \rho_{\text{eff}} L / A_{\text{eff}}$), inducing timing skew on critical clock trees and exacerbating power grid IR drop.

Topographical step heights created by trench dishing degrade scanner depth of focus in subsequent lithography steps. Surface steps exceeding $30\text{--}40\text{ nm}$ consume the allowable focal window of advanced 0.33 NA and 0.55 High-NA EUV lithography systems. When photoresist is coated over severe dishing steps, thickness variations create local dose and focus errors that lead to bridging or pinching defects in subsequent via and metal layers.

Dummy metal fill and smart tile algorithms flatten pattern density to eliminate wide un-supported spans. To combat $w^4$ pad deflection, automated Electronic Design Automation (EDA) layout tools insert floating dummy metal tiles (typically $1\ \mu\text{m} \times 1\ \mu\text{m}$ metal squares) into wide dielectric and power grid openings. By enforcing a uniform metal pattern density ($\rho_{\text{metal}} \approx 30\text{--}50\%$) and restricting maximum un-supported spans to $w \le 2\ \mu\text{m}$, dummy fill prevents the pad from sagging into trenches, reducing total dishing by over $80\%$.

Corrosion inhibitors such as benzotriazole passivate recessed copper surfaces against static chemical etching. Leading-edge copper CMP slurries incorporate chemical corrosion inhibitors such as Benzotriazole ($\text{C}_6\text{H}_5\text{N}_3$, BTA). BTA molecules rapidly chemisorb onto the copper surface, forming an insoluble, hydrophobic polymeric $\text{Cu(I)-BTA}$ passivating monolayer. On high-topography dielectric surfaces, mechanical pad asperities shear off the passivating film to maintain high polish rates; inside dished trenches where the pad cannot touch the recessed metal, the intact BTA protective film halts chemical dissolution.

st=>start: Wafer arrives at CMP Platen 2 with barrier (TaN/Ta) and residual copper
dispense=>operation: Apply high-selectivity barrier slurry with BTA corrosion inhibitor
polish=>operation: Polish barrier layer under low down-force pressure (P ≤ 1.5 psi)
endpoint=>operation: Detect optical reflectance / motor current barrier clearing endpoint
overpolish=>operation: Execute controlled timed over-polish phase (10–15s) with pad conditioning
inspect=>condition: Post-CMP Cu dishing h_dish ≤ 5.0nm and zero barrier residue?
r2r=>operation: Run-to-Run (R2R) adjustment of head zone pressures and slurry flow rate
pass=>end: Certified planar interconnect layer ready for inter-layer dielectric (ILD) PECVD
st->dispense->polish->endpoint->overpolish->inspect
inspect(yes)->pass
inspect(no)->r2r->dispense

Mastering interconnect planarization requires treating CMP dishing as a pad-bending-pattern-density-and-slurry-selectivity lens. By coordinating elastic polyurethane pad stiffness, chemical inhibitor passivation kinetics, automated dummy metal fill synthesis, and multi-zone carrier pressure tuning, semiconductor fabs eliminate topography steps across multi-layer wiring networks. Rigorous dishing suppression ensures that advanced logic and memory circuits achieve target clock frequencies, high electromigration reliability, and zero parametric yield fallout.