DRAM (dynamic random-access memory) stores each bit as charge on a tiny capacitor, gated by a single access transistor — the '1T1C' cell. It is 'dynamic' because that charge leaks away, so the whole array must be read and rewritten periodically (refreshed). The 1T1C design is what makes DRAM the dense, cheap main memory behind almost every system, including the stacked DRAM inside HBM.\n\nA bit is charge on a capacitor, reached through one transistor. To write, the wordline (WL) turns on the access transistor, connecting the storage capacitor to the bitline (BL) so charge flows in or out. To read, the cell dumps its charge onto the bitline and a sense amplifier detects the tiny voltage swing — which destroys the stored value, so DRAM reads are destructive and must be followed by a rewrite. One transistor plus one capacitor per bit is why DRAM is far denser and cheaper per gigabyte than the 6-transistor SRAM cell.\n\nDynamic means it forgets — refresh is the tax. The capacitor holds only about 10 femtofarads and leaks, so every row must be refreshed on the order of every 64 ms or the data decays. Refresh costs power and steals bandwidth, and it gets worse as arrays grow. This is the fundamental tradeoff against SRAM: DRAM wins on density and cost, SRAM wins on speed and needs no refresh, which is exactly why the memory hierarchy uses SRAM for caches and DRAM (and HBM) for capacity.\n\n| | SRAM | DRAM | HBM |\n|---|---|---|---|\n| Cell | 6 transistors | 1T + 1 capacitor | stacked DRAM dies |\n| Refresh | none | required (~64 ms) | required |\n| Density | low | high | high + 3D stacked |\n| Latency | fastest | medium | medium |\n| Role | on-die cache | main memory | bandwidth to accelerators |\n\n``svg\n\n``\n\nScaling DRAM is a capacitor problem. As the cell footprint shrinks toward 4F², the capacitor must still hold roughly the same charge to be sensed reliably — so it grows vertically into deep-trench or tall-pillar 3D structures with extreme aspect ratios, built with high-k dielectrics and buried wordlines. Etching those deep, uniform features is the DRAM-specific scaling wall, and it is a big reason bandwidth now scales by stacking DRAM into HBM rather than by shrinking the cell further.\n\nRead DRAM through a quant lens rather than a 'main memory' lens: the numbers that bind are bandwidth (GB/s) and latency feeding the compute, plus the refresh and activation energy per bit moved. Per the roofline, a memory-bound kernel lives or dies on DRAM/HBM bandwidth, so the design question is how many bytes per second the array can deliver at what energy — a measured throughput budget, not a fixed capacity number.