<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">DRAM — One Transistor, One Capacitor Per Bit</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">charge leaks, so every cell must be refreshed thousands of times per second</text>

  <!-- === LEFT: The 1T1C Cell (physical) === -->
  <text x="130" y="72" fill="#e6edf3" font-size="12" text-anchor="middle" font-weight="600">1T1C Cell</text>

  <!-- Bitline (vertical wire at top) -->
  <line x1="130" y1="82" x2="130" y2="108" stroke="#60a5fa" stroke-width="2"/>
  <text x="145" y="92" fill="#60a5fa" font-size="9">BL (bitline)</text>

  <!-- Access transistor -->
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  <!-- Gate on side -->
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  <text x="85" y="126" fill="#c4b5fd" font-size="8.5" text-anchor="end">Gate</text>
  <text x="130" y="126" fill="#c4b5fd" font-size="9" text-anchor="middle">T</text>
  <!-- Wordline label -->
  <line x1="60" y1="123" x2="100" y2="123" stroke="#a78bfa" stroke-width="1.5"/>
  <text x="55" y="126" fill="#c4b5fd" font-size="8.5" text-anchor="end">WL</text>

  <!-- Connection to capacitor -->
  <line x1="130" y1="138" x2="130" y2="155" stroke="#8b98a5" stroke-width="1.5"/>

  <!-- Capacitor (drawn as physical trench/pillar) -->
  <rect x="115" y="155" width="30" height="60" rx="2" fill="#0d1117" stroke="#f59e0b" stroke-width="1.5"/>
  <!-- Dielectric layer inside -->
  <rect x="120" y="160" width="20" height="50" rx="1" fill="#2a1a0a" stroke="#8a5a2a" stroke-width="0.6"/>
  <!-- Inner electrode -->
  <rect x="125" y="165" width="10" height="40" rx="1" fill="#f59e0b" opacity="0.4"/>
  <text x="130" y="230" fill="#fbbf24" font-size="9" text-anchor="middle">C</text>
  <text x="130" y="243" fill="#a1701a" font-size="8" text-anchor="middle">~20 fF</text>

  <!-- Ground plate -->
  <line x1="105" y1="220" x2="155" y2="220" stroke="#6b7684" stroke-width="1.5"/>
  <line x1="112" y1="224" x2="148" y2="224" stroke="#6b7684" stroke-width="1"/>
  <line x1="118" y1="228" x2="142" y2="228" stroke="#6b7684" stroke-width="0.6"/>

  <!-- Charge indication -->
  <text x="165" y="180" fill="#fbbf24" font-size="8">stored charge</text>
  <text x="165" y="192" fill="#fbbf24" font-size="8">= 1 bit</text>
  <text x="165" y="208" fill="#6b7684" font-size="8">Q = C × V</text>
  <text x="165" y="220" fill="#6b7684" font-size="8">~20 fF × 0.6V</text>

  <!-- Leakage arrow -->
  <path d="M148,185 C165,190 168,170 158,165" fill="none" stroke="#f87171" stroke-width="0.8" stroke-dasharray="2,1"/>
  <text x="178" y="162" fill="#f87171" font-size="7.5">leaks!</text>

  <!-- === MIDDLE: Array Architecture === -->
  <rect x="230" y="70" width="260" height="200" rx="6" fill="#080d14" stroke="#233043" stroke-width="1"/>
  <text x="360" y="88" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">DRAM Array</text>

  <!-- Wordlines (horizontal) -->
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    <line x1="250" y1="110" x2="470" y2="110"/>
    <line x1="250" y1="140" x2="470" y2="140"/>
    <line x1="250" y1="170" x2="470" y2="170"/>
    <line x1="250" y1="200" x2="470" y2="200"/>
    <line x1="250" y1="230" x2="470" y2="230"/>
  </g>
  <text x="245" y="113" fill="#c4b5fd" font-size="8" text-anchor="end">WL₀</text>
  <text x="245" y="143" fill="#c4b5fd" font-size="8" text-anchor="end">WL₁</text>
  <text x="245" y="173" fill="#c4b5fd" font-size="8" text-anchor="end">WL₂</text>
  <text x="245" y="203" fill="#8b98a5" font-size="8" text-anchor="end">⋮</text>
  <text x="245" y="233" fill="#c4b5fd" font-size="8" text-anchor="end">WLₙ</text>

  <!-- Bitlines (vertical) -->
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    <line x1="290" y1="95" x2="290" y2="250"/>
    <line x1="330" y1="95" x2="330" y2="250"/>
    <line x1="370" y1="95" x2="370" y2="250"/>
    <line x1="410" y1="95" x2="410" y2="250"/>
    <line x1="450" y1="95" x2="450" y2="250"/>
  </g>
  <text x="290" y="263" fill="#60a5fa" font-size="8" text-anchor="middle">BL₀</text>
  <text x="330" y="263" fill="#60a5fa" font-size="8" text-anchor="middle">BL₁</text>
  <text x="370" y="263" fill="#60a5fa" font-size="8" text-anchor="middle">BL₂</text>
  <text x="450" y="263" fill="#60a5fa" font-size="8" text-anchor="middle">BLₘ</text>

  <!-- Cells at intersections (small capacitor symbols) -->
  <g>
    <circle cx="290" cy="110" r="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.8"/>
    <circle cx="330" cy="110" r="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.8"/>
    <circle cx="370" cy="140" r="4" fill="#f59e0b" stroke="#fbbf24" stroke-width="0.8"/>
    <circle cx="410" cy="140" r="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.8"/>
    <circle cx="290" cy="170" r="4" fill="#f59e0b" stroke="#fbbf24" stroke-width="0.8"/>
    <circle cx="450" cy="170" r="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.8"/>
    <circle cx="330" cy="200" r="4" fill="#f59e0b" stroke="#fbbf24" stroke-width="0.8"/>
    <circle cx="410" cy="230" r="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.8"/>
    <circle cx="370" cy="230" r="4" fill="#f59e0b" stroke="#fbbf24" stroke-width="0.8"/>
  </g>
  <!-- Legend -->
  <circle cx="260" cy="253" r="3.5" fill="#f59e0b" stroke="#fbbf24" stroke-width="0.6"/>
  <text x="268" y="256" fill="#8b98a5" font-size="7.5">= 1 (charged)</text>
  <circle cx="330" cy="253" r="3.5" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.6"/>
  <text x="338" y="256" fill="#8b98a5" font-size="7.5">= 0 (empty)</text>

  <!-- Sense amplifier at bottom -->
  <rect x="270" y="248" width="190" height="14" rx="2" fill="#1a2a1a" stroke="#34d399" stroke-width="0.8"/>
  <text x="365" y="258" fill="#6ee7b7" font-size="8" text-anchor="middle">Sense Amplifiers (detect µV difference)</text>

  <!-- === RIGHT: Read/Refresh cycle === -->
  <rect x="510" y="70" width="220" height="200" rx="6" fill="#080d14" stroke="#233043" stroke-width="1"/>
  <text x="620" y="88" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">Read + Refresh Cycle</text>

  <!-- Timeline steps -->
  <text x="525" y="108" fill="#a78bfa" font-size="9">1. Activate WL (row open)</text>
  <text x="525" y="124" fill="#60a5fa" font-size="9">2. Charge shares onto BL</text>
  <text x="525" y="140" fill="#34d399" font-size="9">3. Sense amp detects ΔV</text>
  <text x="525" y="156" fill="#fbbf24" font-size="9">4. Amplify to full swing</text>
  <text x="525" y="172" fill="#8b98a5" font-size="9">5. Data out to column mux</text>
  <text x="525" y="188" fill="#f87171" font-size="9">6. Write-back (restore charge)</text>
  <text x="525" y="208" fill="#6b7684" font-size="8.5">— reading is destructive! —</text>

  <!-- Timing -->
  <text x="525" y="230" fill="#e6edf3" font-size="9" font-weight="600">Timing:</text>
  <text x="525" y="246" fill="#8b98a5" font-size="9">tRCD=14ns, tCL=14ns, tRP=14ns</text>
  <text x="525" y="260" fill="#6b7684" font-size="8.5">Refresh: every 32–64 ms (all rows)</text>

  <!-- === BOTTOM: Scaling + generations === -->
  <rect x="30" y="282" width="700" height="80" rx="6" fill="#0b1220" stroke="#233043" stroke-width="1"/>
  <text x="380" y="300" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">DRAM Generations</text>

  <text x="100" y="320" fill="#8b98a5" font-size="9.5" text-anchor="middle">DDR4</text>
  <text x="100" y="334" fill="#6b7684" font-size="8.5" text-anchor="middle">3200 MT/s</text>
  <text x="100" y="346" fill="#6b7684" font-size="8" text-anchor="middle">1.2V</text>

  <text x="230" y="320" fill="#c4b5fd" font-size="9.5" text-anchor="middle" font-weight="600">DDR5</text>
  <text x="230" y="334" fill="#8b98a5" font-size="8.5" text-anchor="middle">6400 MT/s</text>
  <text x="230" y="346" fill="#6b7684" font-size="8" text-anchor="middle">1.1V, on-die ECC</text>

  <text x="370" y="320" fill="#fbbf24" font-size="9.5" text-anchor="middle" font-weight="600">HBM3e</text>
  <text x="370" y="334" fill="#8b98a5" font-size="8.5" text-anchor="middle">9.6 Gbps/pin</text>
  <text x="370" y="346" fill="#6b7684" font-size="8" text-anchor="middle">1024-bit bus, stacked</text>

  <text x="510" y="320" fill="#34d399" font-size="9.5" text-anchor="middle" font-weight="600">LPDDR5X</text>
  <text x="510" y="334" fill="#8b98a5" font-size="8.5" text-anchor="middle">8533 MT/s</text>
  <text x="510" y="346" fill="#6b7684" font-size="8" text-anchor="middle">mobile, 0.5V</text>

  <text x="650" y="320" fill="#f87171" font-size="9.5" text-anchor="middle">GDDR7</text>
  <text x="650" y="334" fill="#8b98a5" font-size="8.5" text-anchor="middle">36 Gbps</text>
  <text x="650" y="346" fill="#6b7684" font-size="8" text-anchor="middle">GPU discrete mem</text>

  <!-- Scaling challenge -->
  <rect x="30" y="372" width="700" height="44" rx="5" fill="#0b1220" stroke="#233043" stroke-width="1"/>
  <text x="380" y="390" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Scaling challenge: capacitor must hold ~20 fF in a shrinking footprint → tall pillar or deep trench</text>
  <text x="380" y="406" fill="#8b98a5" font-size="9.5" text-anchor="middle">High-k dielectric (ZrO₂/HfO₂), ultra-thin electrodes (TiN), aspect ratio 50:1+ at sub-15nm node</text>

  <!-- Key numbers -->
  <text x="380" y="435" fill="#8b98a5" font-size="9.5" text-anchor="middle">Vendors: Samsung, SK hynix, Micron | Total market: ~100B USD/yr | AI drives HBM DRAM demand 5x over DDR</text>

  <text x="380" y="460" fill="#6b7684" font-size="11" text-anchor="middle">DRAM is the simplest storage cell (1T1C) at the hardest scaling challenge — keeping charge in a shrinking bucket.</text>
</svg>
``` (dynamic random-access memory) stores each bit as charge on a tiny capacitor, gated by a single access transistor — the '1T1C' cell. It is 'dynamic' because that charge leaks away, so the whole array must be read and rewritten periodically (refreshed). The 1T1C design is what makes DRAM the dense, cheap main memory behind almost every system, including the stacked DRAM inside HBM.\n\n**A bit is charge on a capacitor, reached through one transistor.** To write, the wordline (WL) turns on the access transistor, connecting the storage capacitor to the bitline (BL) so charge flows in or out. To read, the cell dumps its charge onto the bitline and a sense amplifier detects the tiny voltage swing — which destroys the stored value, so DRAM reads are destructive and must be followed by a rewrite. One transistor plus one capacitor per bit is why DRAM is far denser and cheaper per gigabyte than the 6-transistor SRAM cell.\n\n**Dynamic means it forgets — refresh is the tax.** The capacitor holds only about 10 femtofarads and leaks, so every row must be refreshed on the order of every 64 ms or the data decays. Refresh costs power and steals bandwidth, and it gets worse as arrays grow. This is the fundamental tradeoff against SRAM: DRAM wins on density and cost, SRAM wins on speed and needs no refresh, which is exactly why the memory hierarchy uses SRAM for caches and DRAM (and HBM) for capacity.\n\n| | SRAM | DRAM | HBM |\n|---|---|---|---|\n| Cell | 6 transistors | 1T + 1 capacitor | stacked DRAM dies |\n| Refresh | none | required (~64 ms) | required |\n| Density | low | high | high + 3D stacked |\n| Latency | fastest | medium | medium |\n| Role | on-die cache | main memory | bandwidth to accelerators |\n\n```svg\n<svg viewBox="0 0 1000 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif">\n  <rect x="0" y="0" width="1000" height="470" rx="14" fill="#1d1c1a"/>\n  <text x="36" y="38" fill="#e8e6f7" font-size="20" font-weight="600">DRAM — one transistor + one capacitor per bit, and it leaks (so it must refresh)</text>\n\n  <!-- ===== 1T1C cell ===== -->\n  <text x="250" y="76" fill="#c9c3f2" font-size="14" text-anchor="middle">1T1C cell: access transistor gates charge onto a storage capacitor</text>\n\n  <!-- bitline -->\n  <line x1="150" y1="110" x2="150" y2="170" stroke="#e0913a" stroke-width="2.5"/>\n  <text x="150" y="104" fill="#f0d9b5" font-size="12" text-anchor="middle">bitline (BL)</text>\n  <!-- access transistor -->\n  <rect x="128" y="170" width="44" height="30" rx="4" fill="#0f6b5a" stroke="#1f9e85" stroke-width="1.6"/>\n  <text x="150" y="190" fill="#bff0e4" font-size="13" text-anchor="middle">M</text>\n  <!-- wordline into gate -->\n  <line x1="60" y1="185" x2="128" y2="185" stroke="#d33f3f" stroke-width="2.5"/>\n  <text x="70" y="176" fill="#d33f3f" font-size="12">wordline (WL)</text>\n  <!-- to capacitor -->\n  <line x1="150" y1="200" x2="150" y2="240" stroke="#6f6f6a" stroke-width="1.8"/>\n  <!-- capacitor plates -->\n  <line x1="118" y1="240" x2="182" y2="240" stroke="#7d70e0" stroke-width="4"/>\n  <line x1="118" y1="256" x2="182" y2="256" stroke="#7d70e0" stroke-width="4"/>\n  <text x="150" y="284" fill="#c9c3f2" font-size="13" text-anchor="middle">C ≈ 10 fF</text>\n  <line x1="150" y1="256" x2="150" y2="296" stroke="#6f6f6a" stroke-width="1.8"/>\n  <line x1="130" y1="296" x2="170" y2="296" stroke="#4a4a47" stroke-width="3"/>\n  <text x="150" y="312" fill="#8a8a86" font-size="13" text-anchor="middle">V_plate</text>\n\n  <!-- leakage + refresh loop (routed clear of the cell) -->\n  <path d="M 182 244 C 260 220 280 170 330 158" fill="none" stroke="#d33f3f" stroke-width="2" stroke-dasharray="4 3"/>\n  <polygon points="330,158 338,157 333,165" fill="#d33f3f"/>\n  <text x="300" y="212" fill="#d33f3f" font-size="13">charge leaks away</text>\n  <text x="348" y="150" fill="#f0d9b5" font-size="13" font-weight="600">refresh every ~64 ms</text>\n  <text x="348" y="170" fill="#8a8a86" font-size="13">read + rewrite the whole array;</text>\n  <text x="348" y="187" fill="#8a8a86" font-size="13">the bit is destroyed on read.</text>\n  <text x="348" y="252" fill="#c9c3f2" font-size="12">stored charge = the bit</text>\n\n  <text x="60" y="360" fill="#d4d4d0" font-size="12.5">Only 1 transistor + 1 capacitor per bit → very dense &amp; cheap per GB,</text>\n  <text x="60" y="380" fill="#d4d4d0" font-size="12.5">but destructive read, refresh overhead, and higher latency than SRAM.</text>\n\n  <!-- divider -->\n  <line x1="500" y1="70" x2="500" y2="345" stroke="#3a3a37" stroke-width="1.2" stroke-dasharray="4 4"/>\n\n  <!-- ===== capacitor scaling ===== -->\n  <text x="720" y="76" fill="#c9c3f2" font-size="14" text-anchor="middle">The capacitor must keep its charge as the cell shrinks</text>\n  <line x1="560" y1="300" x2="900" y2="300" stroke="#4a4a47" stroke-width="1.4"/>\n  <rect x="578" y="230" width="44" height="70" rx="3" fill="#173d34" stroke="#1f9e85" stroke-width="1.6"/><text x="600" y="318" fill="#8a8a86" font-size="13" text-anchor="middle">old node</text><text x="600" y="333" fill="#bff0e4" font-size="13" text-anchor="middle">6F²</text><text x="600" y="222" fill="#e0913a" font-size="12" text-anchor="middle">7:1</text><rect x="705" y="190" width="30" height="110" rx="3" fill="#173d34" stroke="#1f9e85" stroke-width="1.6"/><text x="720" y="318" fill="#8a8a86" font-size="13" text-anchor="middle">newer</text><text x="720" y="333" fill="#bff0e4" font-size="13" text-anchor="middle">4F²</text><text x="720" y="182" fill="#e0913a" font-size="12" text-anchor="middle">11:1</text><rect x="829" y="150" width="22" height="150" rx="3" fill="#173d34" stroke="#1f9e85" stroke-width="1.6"/><text x="840" y="318" fill="#8a8a86" font-size="13" text-anchor="middle">leading</text><text x="840" y="333" fill="#bff0e4" font-size="13" text-anchor="middle">≈4F² 3D</text><text x="840" y="142" fill="#e0913a" font-size="12" text-anchor="middle">15:1</text>\n  <text x="720" y="360" fill="#f0d9b5" font-size="12.5" text-anchor="middle">Smaller footprint, same ~10 fF → taller, higher-aspect-ratio 3D capacitor.</text>\n  <text x="720" y="380" fill="#8a8a86" font-size="13" text-anchor="middle">Etching deep, uniform trenches is the hard, DRAM-specific scaling limit.</text>\n</svg>\n```\n\n**Scaling DRAM is a capacitor problem.** As the cell footprint shrinks toward 4F², the capacitor must still hold roughly the same charge to be sensed reliably — so it grows vertically into deep-trench or tall-pillar 3D structures with extreme aspect ratios, built with high-k dielectrics and buried wordlines. Etching those deep, uniform features is the DRAM-specific scaling wall, and it is a big reason bandwidth now scales by stacking DRAM into HBM rather than by shrinking the cell further.\n\nRead DRAM through a quant lens rather than a 'main memory' lens: the numbers that bind are bandwidth (GB/s) and latency feeding the compute, plus the refresh and activation energy per bit moved. Per the roofline, a memory-bound kernel lives or dies on DRAM/HBM bandwidth, so the design question is how many bytes per second the array can deliver at what energy — a measured throughput budget, not a fixed capacity number.